IEEE International Symposium on Information Theory (ISIT)

Integrated parallel interleaved concatenation for lowering error floors of LDPC codes

Naoaki Kokubun, Hironori Uchikawa

Published Jul 1, 2016• 1 citation

Abstract

In order to suppress error floors of low density parity check (LDPC) codes, we study a parallel concatenation scheme with an intermediate single parity check (SPC) code and interleavers. The interleavers of the concatenation play an important role to lower error floors, because it is highly possible that interleaved bits in a trapping set are not to be in error even if the bits in the trapping set are originally in error. For quasi-cyclic LDPC codes, our simulation results confirm that the integrated parallel interleaved concatenation with circulant-size cyclic-shift interleavers improves error-floor performance, and it is better than serial concatenation schemes with BCH codes. If a decoder can afford to accommodate higher-hardware complexity, the decoding performance of our scheme improves so that the error floor can be lowered further.

DOI: 10.1109/isit.2016.7541852

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