Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

High Speed Low Error Floor Hardware Implementation and Fast and Accurate Error Floor Estimation of LDPC Decoders

Sina Tolouei

Published Jan 1, 2014• 2 citations
Publisher

Abstract

This thesis explores hardware implementation of low error floor and high speed low-density parity-check (LDPC) decoders.At first, a novel partially-parallel implementation of a protograph-based quasi-cyclic (QC) LDPC decoder, using a new column-layered message-passing schedule is presented.A new design for serial-input check nodes and switch networks, results in lower hardware complexity while having a higher throughput and comparable latency in comparison with all existing partiallyparallel architectures.Thereafter, we introduce a multi-step scheme for the input quantization of message-passing decoders for LDPC codes.The scheme is based on successive requantization and re-decoding of the input blocks that cause the decoder to be trapped in a trapping set, until the decoding is successful or a maximum number of requantization/re-decodings is reached.The proposed scheme, which is applicable to both regular and irregular codes, lowers the error floor significantly at the cost of small increase in complexity, memory and latency.Furthermore, to facilitate the process of code design and performance evaluation in the error floor region, we design a fast and accurate technique to estimate the error floor of variable-regular LDPC codes under quantized iterative decoding algorithms.This technique, which is based on enumerating the dominant elementary trapping sets of the code, provides significant improvement over existing methods in terms of speed and accuracy.Finally, we examine the harmfulness of trapping sets of variable-regular LDPC codes for soft-decision iterative decoding algorithms.We show that, other than the size of a trapping set, the number of unsatisfied check nodes and the trapping set's topological properties, the position of its subgraph in the Tanner graph of the code can also have an effect on its harmfulness.We also examine dominant trapping sets iii of the quantized min-sum (MS) decoding algorithm and two of its variants (offset-MS and MS with successive relaxation (SR)), for both regular and irregular LDPC codes.We show that the distribution of dominant trapping sets of these algorithms is similar for regular codes and different for irregular codes.Based on these results, we evaluate the error floor performance of a decoder, consisting of MS, offset-MS and SR-MS decoding algorithms working in parallel.First, I would like to thank my supervisor, Professor Amir H. Banihashemi for leading and encouraging me during my research.When I started as his M.A.Sc.student nine years ago, my dream was to acquire a set of skills.Amir helped me to achieve them with invaluable advice and excellent guidance.I would also like to thank M. Samy Hosny, the CEO of SiloconPro Inc. for supporting my research and providing me with his professional experience.I can not express my appreciation to my wonderful wife

DOI
10.22215/etd/2014-10497

Related papers

Error Floor Analysis of Quasi-Cyclic LDPC and Spatially Coupled-LDPC Codes and Construction of Codes with Low Error Floor

Sima Naseri

Forward error-correcting (FEC) codes play an important role in transmitting data with extremely high reliability through modern communication systems.Many applications such as optical communication channels require a very low error rate when transmitting data.In this thesis, we study the design and analysis of low-density parity-check (LDPC) codes in general and spatially coupled (SC) LDPC codes in particular.At first, we analyze the error floor performance of finite-length protographbased spatially coupled LDPC codes in terms of their design parameters.We conduct a comprehensive analysis to show that the parameter syndrome former memory (m) plays the main role in the average number of cycles and trapping sets in the Tanner graph of finite-length SC-LDPC codes.This, in fact, gives an insight into the error floor performance of protograph-based SC-LDPC codes, and demonstrates the superiority of these codes in the error floor region, compared to their block code counterparts.To complement the theoretical analysis conducted in the first stage of this research, we develop efficient design techniques for the construction of high-performance quasi-cyclic (QC)-LDPC and SC-LDPC codes, as the second part of the research.Our design approach is basically aimed at improving the performance of finite-length (SC) LDPC codes while maintaining the decoder complexity and latency small.The improvement in error floor is achieved by minimizing (elimination of) the most harmful trapping set (TS)s.In this regard, we present two design approaches: i) imposing simple conditions on the small cycles to result in the elimination of specific classes of trapping sets, ii) developing a search-based design technique such that specific trapping sets are targeted for minimization/elimination through the algorithm.Our constructed QC-LDPC and time-invariant SC-LDPC codes are superior to the stateof-the-art both in terms of their error floor performance and their low decoding latency and complexity.Finally, we look into the design of finite-length time-invariant QC SC-LDPC codes iii I would like to take this opportunity to express my sincere gratitude to my supervisor, Prof. Amir H. Banihashemi, for his invaluable guidance, continuous support and excellent mentorship during the course of my PhD studies.His immense knowledge and supervision always steered me to the right direction during this journey.Besides my supervisor, I would like to thank my committee members for their helpful comments and feedback on this thesis, and for their generosity in contributing their time to serve on my dissertation defense.I would like to mention the government of Ontario in acknowledgment of the Ontario Trillium Scholarship which pledged an ample

•Jan 1, 2021•2 citations

Construction of QC-LDPC Codes with Low Error Floor by Efficient Systematic Search and Elimination of Trapping Sets

Bashirreza Karimi

In this thesis, we propose a systematic design of binary protograph-based quasi-cyclic (QC) low-density parity-check (LDPC) codes with low error floor.We first characterize the trapping sets of such codes and demonstrate, using edge coloring techniques, that the QC structure of the code eliminates some of the trapping set structures that can exist in a code with the same degree distribution and girth but lacking the QC structure.Based on this characterization, our design aims at eliminating a targeted collection of trapping sets.Considering the parent/child relationship between the structures of the collection, we search for and eliminate those trapping sets that are in the collection but are not a child of any other trapping set in the collection.An efficient layered algorithm is designed for the search of these targeted trapping sets.Compared to the existing codes in the literature, the designed codes are superior in the sense that they are free of the same collection of trapping sets while having a smaller block length, or a larger collection of trapping sets while having the same block length.In addition, the efficiency of the search algorithm makes it possible to design codes with larger degrees which are free of trapping sets within larger ranges compared to the state-of-the-art.Moreover, we design finite-length binary irregular protograph-based QC-LDPC codes with good waterfall performance and low error floor.To achieve a low error floor, we eliminate a targeted set of dominant elementary trapping sets (ETS) L in the Tanner graph of the code.This is a more challenging task since the variety of problematic structures is much larger than that of regular codes.For a given rate and girth, the codes are designed to be free of the largest set of problematic ETSs for a given block length, or to have the shortest block length while a given set of ETSs is avoided.The design is based on a search algorithm that identifies whether any instance of any structure within L exists in the Tanner graph of the constructed code or not.The search algorithm performs this task with minimal complexity, making it feasible to construct practical codes by running the search algorithm a large numberiiiFirst, I would like to thank my supervisor, Professor Amir H. Banihashemi for leading and encouraging me during my research.His guidance helped me in all the time of research and writing of this thesis.Thanks must also go to my committee members for their helpful suggestions and discussions.I can not express my appreciation to my wonderful wife, Arefeh who devoted her never ending love to me and was my partner towards success.I also appreciate the love and support of my family,

•Jan 1, 2021•2 citations

Design and implementation of decoders for error correction in high-speed communication systems.

Joan Marc Català Pérez

This thesis is focused on the design and implementation of binary low-density parity-check (LDPC) code decoders for high-speed modern communication systems. The basic of LDPC codes and the performance and bottlenecks, in terms of complexity and hardware efficiency, of the main soft-decision and hard-decision decoding algorithms (such as Min-Sum, Optimized 2-bit Min-Sum and Reliability-based iterative Majority-Logic) are analyzed. The complexity and performance of those algorithms are improved to allow efficient hardware architectures.\n\nA new decoding algorithm called One-Minimum Min-Sum is proposed. It reduces considerably the complexity of the check node update equations of the Min-Sum algorithm. The second minimum is estimated from the first minimum value by a means of a linear approximation that allows a dynamic adjustment. The Optimized 2-bit Min-Sum algorithm is modified to initialize it with the complete LLR values and to introduce the extrinsic information in the messages sent from the variable nodes. Its variable node equation is reformulated to reduce its complexity. Both algorithms were tested for the (2048,1723) RS-based LDPC code and (16129,15372) LDPC code using an FPGA-based hardware emulator. They exhibit BER performance very close to Min-Sum algorithm and do not introduce early error-floor. \n\nIn order to show the hardware advantages of the proposed algorithms, hardware decoders were implemented in a 90 nm CMOS process and FPGA devices based on two types of architectures: full-parallel and partial-parallel one with horizontal layered schedule. The results show that the decoders are more area-time efficient than other published decoders and that the low-complexity of the Modified Optimized 2-bit Min-Sum allows the implementation of 10 Gbps decoders in current FPGA devices. \n\nFinally, a new hard-decision decoding algorithm, the Historical-Extrinsic Reliability-Based Iterative Decoder, is presented. This algorithm introduces the new idea of considering hard-decision votes as soft-decision to compute the extrinsic information of previous iterations. It is suitable for high-rate codes and improves the BER performance of the previous RBI-MLGD algorithms, with similar complexity.

•Jul 7, 2017•0 citations

Code-Independent Error Floor Estimation Techniques for Flooding and Layered Decoders of LDPC Codes

Ali Farsiabi

Finite-length low-density parity-check (LDPC) codes under iterative message passing algorithms suffer from error floor, i.e., as the channel quality improves, at some point, the error rate does not decrease as fast as its initial rate of decrease.The literature on the error floor analysis/estimation of LDPC codes can be, in general, partitioned into two main categories.The first category requires the full knowledge of the parity-check matrix or Tanner graph of the code to estimate the error floor.The second category, on the other hand, is code-independent, in that, rather than the full knowledge of the code's Tanner graph, these techniques only require the multiplicity and topology of harmful substructures of the Tanner graph, referred to as trapping sets (TSs), and possibly the degree distributions of the graph, to estimate the error floor.The proposed techniques in this thesis fit within the second category.The linear state-space model is a well-known code-independent method to estimate the contribution of a trapping set structure to the error floor of low-density paritycheck codes.In this thesis we first provide an in-depth analysis of this method by incorporating a more accurate model for the incoming messages to the TS structure that takes into account the randomness and the correlation among such messages.Based on this analysis, we demonstrate that both randomness and correlation result in the over-estimation of the failure probability of the TS.We then propose an alternate code-independent technique for the error floor estimation of iterative LDPC decoders that can accurately estimate the contribution of different TS structures in the error floor.Compared to the linear state-space model, the proposed method is not only more accurate, but also more general, in that, it is applicable to any saturating iterative message-passing decoder, symmetrically quantized or unquantized, over any memoryless binary-input output-symmetric channel.To the best of our knowledge, all the existing work on the theoretical analysis of error floor is limited to two-phase message passing algorithms, also known as flooding or parallel schedule.There are however a variety of message passing schedules which iii 4.5 The steps of constructing the digraph D l (S) of the (5, 3) LETS for a layered decoder from the flooding digraph D f (S).(The colors (edge types) red (dotted), blue (dashed) and purple (dash-dotted) represent L 1 , L 2 and L 3 , respectively.) . . . . . . . . . . . . . . . . . . . . . .69 4.6 QC-LDPC codes used for simulations.The entries of the matrices, that are not equal to -1, represent the right circular shift of the identity matrix to create the corresponding block of the parity-check matrix.The -1 entries represent zero blocks. . . . . . . . . . . . . . . . . . .80 4.7 Simulation and estimation results of C 1 for different saturation levels.The maximum number of iterations I max = 30. . . . . . . . . . . . .81 4.8 The (5, 5) LETS structure of C 1 in which the row layers for different CNs are shown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 4.9 The approximate estimate of the failure probability of the (5, 5) LETS of C 1 for various row layered schedules at E b /N 0 = 6 dB and saturation level 31.75.The schedules are sorted based on r. . . . . . . . . . . .83 4.10 The simulation and estimation results of C 1 for different row schedules.(The saturation level is 31.75, and the maximum number of iterations for layered schedules and the flooding schedule are set to 30 and 60, respectively.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 4.11 The effect of various row layered schedules on the failure probability of different classes of LETSs in C 2 (E b /N 0 = 6 dB, saturation level 15.75).85 4.12 The effect of various row layered schedules on the total FER of C 2 (E b /N 0 = 6 dB, saturation level 15.75). . . . . . . . . . . . . . . . . .85 4.13 The error estimation of the ten (7, 1) LETS groups of C 2 for the two schedules (1, 2, 3, 4, 5, 6) and (4, 1, 5, 2, 3, 6) (saturation level 15.75). .86 4.14 Simulation and estimation results of C 2 for the two schedules (1, 2, 3, 4, 5, 6) and (4, 1, 5, 2, 3, 6) (saturation level 15.75,I max = 30). .87 5.1 A labelled (5,3) LETS of the Tanner (155, 64) code in which the flow of the state variables are shown.The VNs, mis-satisfied CNs and unsatisfied CNs are shown by black circles, white squares and gray squares, respectively.The directed edges related to the layers number 1, 2 and 3 are represented by red, blue and purple colors, respectively.93 xiii 5.2 The VNs v 1 and v 4 related to Fig. 5.1 with the mis-satisfied CN c j connecting them.Figures (a) and (b) are related to virtual VNs, v k and v k , that are used during the update of VNs from layers L 1 and L 3 , respectively.. . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 5.3 Base graph of Example 16: The solid (red), dashed (green), dotted (blue) and dashed-dotted (purple) arrows, respectively, illustrate the updating order which the column layered decoder perform, accordingly.109 5.4 The error estimation related to (5, 5) LETS of C 1 for various column layered schedules at E b /N 0 = 6 dB.All the schedules result in the same dominant eigenvalue of the layered transition matrix, r = 16.9536.The saturation level is 15.75. . . . . . . . . . . . . . . . . . . . . . . . . .111 5.5 The simulation and estimation results related to code C 1 showing the effect of different schedules.The saturation level is 15.75 and the maximum number of iterations is 30. . . . . . . . . . . . . . . . . . .111 5.6 The simulation and estimation results related to code C 2 showing the effect of different schedules.The saturation level is 15.75.The maximum number of iterations is 30. . . . . . . . . . . . . . . . . . . . .113 6.1 The histogram of the conditional error indicator function of a (5, 5) ETS of (640, 192) QC-LDPC code [3] at different iterations. . . . . .128 6.2 Simulation and estimation results for C 1 decoded by SPA over the AWGN channel (I max = 200). . . . . . . . . . . . . . . . . . . . . . .134 6.3 Simulation and extrapolated estimation results for C 1 decoded by SPA over the AWGN channel (I max = 200).The extrapolated curves are obtained based on the results at E b /N 0 = 4.5 dB . . . . . . . . . . . .136 6.4 Simulation and estimation results for C 2 decoded by SPA over the AWGN channel (I max = 200, C th = 25).The extrapolation in DSLM E is based on the results at E b /N 0 = 2.75 dB. . . . . . . . . . . . . . . .136 6.5 Simulation and estimation results for C 3 decoded by SPA over the AWGN channel (I max = 200).The extrapolation in DSLM E is based on the results at E b /N 0 = 4.5 dB. . . . . . . .

•Jan 1, 2020•5 citations

Improving the Error Floor Performance of LDCP Codes with Better Codes and Better Decoders

Dung Viet Nguyen

Error correcting codes are used in virtually all communication systems to ensure reliable transmission of information. In 1948, Shannon established an upper-bound on the maximum rate at which information can be transmitted reliably over a noisy channel. Reliably transmitting information with a rate close to this theoretical limit, known as the channel capacity, has been the goal of channel coding scientists for the last five decades. The rediscovery of low-density parity-check (LDPC) codes in the 1990s added much-renewed excitement in the coding community. LDPC codes are interesting because they can approach channel capacity under sub-optimum decoding algorithms whose complexity is linear in the code length. Unsurprisingly, LDPC codes quickly attained their popularity in practical applications such as magnetic storage, wireless and optical communications. One, if not the most, important and challenging problem in LDPC code research is the study and analysis of the error floor phenomenon. This phenomenon is described as an abrupt degradation in the frame error rate performance of LDPC codes in the high signal-to-noise ratio region. Error floor is harmful because its presence prevents the LDPC decoder from reaching very low probability of decoding failure, an important requirement for many applications. Not long after the rediscovery of LDPC codes, scientists established that error floor is caused by certain harmful structures, most commonly known as trapping sets, in the Tanner representation of a code. Since then, the study of error floor mostly consists of three major problems: 1) estimating error floor; 2) constructing LDPC codes with low error floor and 3) designing decoders that are less susceptible to error floor. Although some parts of this dissertation can be used as important elements in error floor estimation, our main contributions are a novel method for constructing LDPC codes with low error floor and a novel class of low complexity decoding algorithms that can collectively alleviate error floor. These contributions are summarized as follows. A method to construct LDPC codes with low error floors on the binary symmetric channel is presented. Codes are constructed so that their Tanner graphs are free of certain small trapping sets. These trapping sets are selected from the Trapping Set Ontology for the Gallager A/B decoder. They are selected based on their relative harmfulness for a given decoding algorithm. We evaluate the relative harmfulness of different trapping sets for the sum-product algorithm by using the topological relations among them and by analyzing the decoding failures on one trapping set in the presence or absence of other trapping sets. We apply this method to construct structured LDPC codes. To facilitate the discussion, we give a new description of structured LDPC codes whose parity-check matrices are arrays of permutation matrices. This description uses Latin squares to define a set of permutation matrices that have disjoint support and to derive a simple necessary and sufficient condition for the Tanner graph of a code to be free of four-cycles. A new class of bit flipping algorithms for LDPC codes over the binary symmetric channel is proposed. Compared to the regular (parallel or serial) bit flipping algorithms, the proposed algorithms employ one additional bit at a variable node to represent its "strength." The introduction of this additional bit allows an increase in the guaranteed error correction capability. An additional bit is also employed at a check node to capture information which is beneficial to decoding. A framework for failure analysis and selection of two-bit bit flipping algorithms is provided. The main component of this framework is the (re)definition of trapping sets, which are the most "compact" Tanner graphs that cause decoding failures of an algorithm. A recursive procedure to enumerate trapping sets is described. This procedure is the basis for selecting a collection of algorithms that work well together. It is demonstrated that decoders which employ a properly selected group of the proposed algorithms operating in parallel can offer high speed and low error floor decoding.

•Jan 1, 2012•1 citation

An Absorbing Set Analysis of Quantized LDPC Decoders

Homayoon Hatami

The performance of low-density parity-check (LDPC) codes at high signal-to- noise ratios (SNRs) is known to be limited by the presence of certain sub-graphs that exist in the Tanner graph representation of the code, for example trapping sets and absorbing sets. This dissertation derives a lower bound on the frame error rate (FER) of any LDPC code containing a given problematic sub-graph, assuming a particular iterative message passing (MP) decoder and decoder quantization. A crucial aspect of the lower bound is that it is code-independent, in the sense that it can be derived based only on a problematic sub-graph and then applied to any code containing it. Due to the complexity of evaluating the exact bound, assumptions are proposed to approximate it, from which we can estimate decoder performance. For LDPC codes, the attenuated min-sum algorithm (AMSA) and the offset min- sum algorithm (OMSA) are known to outperform the conventional min-sum algorithm (MSA) at low SNRs, i.e., in the waterfall region of the FER curve. This dis- sertation demonstrates that, for quantized LDPC decoders, the AMSA and OMSA underperform the MSA at high SNRs, i.e., in the error floor region of the FER curve, and that the MSA, AMSA, and OMSA all suffer from a relatively high error floor. Therefore, we introduce a novel modification of the MSA for quantized decoding of LDPC codes, called the threshold attenuated min-sum algorithm (TAMSA) (or the threshold offset min-sum algorithm (TOMSA)) with the aim of outperforming the MSA, AMSA, and OMSA at both low and high SNRs. The new decoding algorithm is designed based on the common assumption that trapping sets are the major cause of the error floor for quantized LDPC decoders, and it is shown to reduce the error probability associated with these problematic graphic objects. The lower bound analysis tool noted above is then used to verify the effectiveness of the new TAMSA (TOMSA) and also to assist in finding its optimum design parameters. We also show that the implementation complexity of the TAMSA (TOMSA) is only slightly higher than that of the AMSA or OMSA. Finally, we extend the lower bound to sliding window (SW) decoding of spatially coupled LDPC (SC-LDPC) codes. Additionally, we show that the performance of the TAMSA (TOMSA) is better than that of the MSA, AMSA, and OMSA for SW.

•Nov 16, 2022•0 citations
This thesis explores hardware implementation of low error floor and high speed low-density parity-check (LDPC) decoders.At first, a novel partially-parallel implementation of a protograph-based quasi-cyclic (QC) LDPC decoder, using a new column-layered message-passing schedule is presented.A new design for serial-input check nodes and switch networks, results in lower hardware complexity while having a higher throughput and comparable latency in comparison with all existing partiallyparallel architectures.Thereafter, we introduce a multi-step scheme for the input quantization of message-passing decoders for LDPC codes.The scheme is based on successive requantization and re-decoding of the input blocks that cause the decoder to be trapped in a trapping set, until the decoding is successful or a maximum number of requantization/re-decodings is reached.The proposed scheme, which is applicable to both regular and irregular codes, lowers the error floor significantly at the cost of small increase in complexity, memory and latency.Furthermore, to facilitate the process of code design and performance evaluation in the error floor region, we design a fast and accurate technique to estimate the error floor of variable-regular LDPC codes under quantized iterative decoding algorithms.This technique, which is based on enumerating the dominant elementary trapping sets of the code, provides significant improvement over existing methods in terms of speed and accuracy.Finally, we examine the harmfulness of trapping sets of variable-regular LDPC codes for soft-decision iterative decoding algorithms.We show that, other than the size of a trapping set, the number of unsatisfied check nodes and the trapping set's topological properties, the position of its subgraph in the Tanner graph of the code can also have an effect on its harmfulness.We also examine dominant trapping sets iii of the quantized min-sum (MS) decoding algorithm and two of its variants (offset-MS and MS with successive relaxation (SR)), for both regular and irregular LDPC codes.We show that the distribution of dominant trapping sets of these algorithms is similar for regular codes and different for irregular codes.Based on these results, we evaluate the error floor performance of a decoder, consisting of MS, offset-MS and SR-MS decoding algorithms working in parallel.First, I would like to thank my supervisor, Professor Amir H. Banihashemi for leading and encouraging me during my research.When I started as his M.A.Sc.student nine years ago, my dream was to acquire a set of skills.Amir helped me to achieve them with invaluable advice and excellent guidance.I would also like to thank M. Samy Hosny, the CEO of SiloconPro Inc. for supporting my research and providing me with his professional experience.I can not express my appreciation to my wonderful wife
Forward error-correcting (FEC) codes play an important role in transmitting data with extremely high reliability through modern communication systems.Many applications such as optical communication channels require a very low error rate when transmitting data.In this thesis, we study the design and analysis of low-density parity-check (LDPC) codes in general and spatially coupled (SC) LDPC codes in particular.At first, we analyze the error floor performance of finite-length protographbased spatially coupled LDPC codes in terms of their design parameters.We conduct a comprehensive analysis to show that the parameter syndrome former memory (m) plays the main role in the average number of cycles and trapping sets in the Tanner graph of finite-length SC-LDPC codes.This, in fact, gives an insight into the error floor performance of protograph-based SC-LDPC codes, and demonstrates the superiority of these codes in the error floor region, compared to their block code counterparts.To complement the theoretical analysis conducted in the first stage of this research, we develop efficient design techniques for the construction of high-performance quasi-cyclic (QC)-LDPC and SC-LDPC codes, as the second part of the research.Our design approach is basically aimed at improving the performance of finite-length (SC) LDPC codes while maintaining the decoder complexity and latency small.The improvement in error floor is achieved by minimizing (elimination of) the most harmful trapping set (TS)s.In this regard, we present two design approaches: i) imposing simple conditions on the small cycles to result in the elimination of specific classes of trapping sets, ii) developing a search-based design technique such that specific trapping sets are targeted for minimization/elimination through the algorithm.Our constructed QC-LDPC and time-invariant SC-LDPC codes are superior to the stateof-the-art both in terms of their error floor performance and their low decoding latency and complexity.Finally, we look into the design of finite-length time-invariant QC SC-LDPC codes iii I would like to take this opportunity to express my sincere gratitude to my supervisor, Prof. Amir H. Banihashemi, for his invaluable guidance, continuous support and excellent mentorship during the course of my PhD studies.His immense knowledge and supervision always steered me to the right direction during this journey.Besides my supervisor, I would like to thank my committee members for their helpful comments and feedback on this thesis, and for their generosity in contributing their time to serve on my dissertation defense.I would like to mention the government of Ontario in acknowledgment of the Ontario Trillium Scholarship which pledged an ample
In this thesis, we propose a systematic design of binary protograph-based quasi-cyclic (QC) low-density parity-check (LDPC) codes with low error floor.We first characterize the trapping sets of such codes and demonstrate, using edge coloring techniques, that the QC structure of the code eliminates some of the trapping set structures that can exist in a code with the same degree distribution and girth but lacking the QC structure.Based on this characterization, our design aims at eliminating a targeted collection of trapping sets.Considering the parent/child relationship between the structures of the collection, we search for and eliminate those trapping sets that are in the collection but are not a child of any other trapping set in the collection.An efficient layered algorithm is designed for the search of these targeted trapping sets.Compared to the existing codes in the literature, the designed codes are superior in the sense that they are free of the same collection of trapping sets while having a smaller block length, or a larger collection of trapping sets while having the same block length.In addition, the efficiency of the search algorithm makes it possible to design codes with larger degrees which are free of trapping sets within larger ranges compared to the state-of-the-art.Moreover, we design finite-length binary irregular protograph-based QC-LDPC codes with good waterfall performance and low error floor.To achieve a low error floor, we eliminate a targeted set of dominant elementary trapping sets (ETS) L in the Tanner graph of the code.This is a more challenging task since the variety of problematic structures is much larger than that of regular codes.For a given rate and girth, the codes are designed to be free of the largest set of problematic ETSs for a given block length, or to have the shortest block length while a given set of ETSs is avoided.The design is based on a search algorithm that identifies whether any instance of any structure within L exists in the Tanner graph of the constructed code or not.The search algorithm performs this task with minimal complexity, making it feasible to construct practical codes by running the search algorithm a large numberiiiFirst, I would like to thank my supervisor, Professor Amir H. Banihashemi for leading and encouraging me during my research.His guidance helped me in all the time of research and writing of this thesis.Thanks must also go to my committee members for their helpful suggestions and discussions.I can not express my appreciation to my wonderful wife, Arefeh who devoted her never ending love to me and was my partner towards success.I also appreciate the love and support of my family,
This thesis is focused on the design and implementation of binary low-density parity-check (LDPC) code decoders for high-speed modern communication systems. The basic of LDPC codes and the performance and bottlenecks, in terms of complexity and hardware efficiency, of the main soft-decision and hard-decision decoding algorithms (such as Min-Sum, Optimized 2-bit Min-Sum and Reliability-based iterative Majority-Logic) are analyzed. The complexity and performance of those algorithms are improved to allow efficient hardware architectures.\n\nA new decoding algorithm called One-Minimum Min-Sum is proposed. It reduces considerably the complexity of the check node update equations of the Min-Sum algorithm. The second minimum is estimated from the first minimum value by a means of a linear approximation that allows a dynamic adjustment. The Optimized 2-bit Min-Sum algorithm is modified to initialize it with the complete LLR values and to introduce the extrinsic information in the messages sent from the variable nodes. Its variable node equation is reformulated to reduce its complexity. Both algorithms were tested for the (2048,1723) RS-based LDPC code and (16129,15372) LDPC code using an FPGA-based hardware emulator. They exhibit BER performance very close to Min-Sum algorithm and do not introduce early error-floor. \n\nIn order to show the hardware advantages of the proposed algorithms, hardware decoders were implemented in a 90 nm CMOS process and FPGA devices based on two types of architectures: full-parallel and partial-parallel one with horizontal layered schedule. The results show that the decoders are more area-time efficient than other published decoders and that the low-complexity of the Modified Optimized 2-bit Min-Sum allows the implementation of 10 Gbps decoders in current FPGA devices. \n\nFinally, a new hard-decision decoding algorithm, the Historical-Extrinsic Reliability-Based Iterative Decoder, is presented. This algorithm introduces the new idea of considering hard-decision votes as soft-decision to compute the extrinsic information of previous iterations. It is suitable for high-rate codes and improves the BER performance of the previous RBI-MLGD algorithms, with similar complexity.
Finite-length low-density parity-check (LDPC) codes under iterative message passing algorithms suffer from error floor, i.e., as the channel quality improves, at some point, the error rate does not decrease as fast as its initial rate of decrease.The literature on the error floor analysis/estimation of LDPC codes can be, in general, partitioned into two main categories.The first category requires the full knowledge of the parity-check matrix or Tanner graph of the code to estimate the error floor.The second category, on the other hand, is code-independent, in that, rather than the full knowledge of the code's Tanner graph, these techniques only require the multiplicity and topology of harmful substructures of the Tanner graph, referred to as trapping sets (TSs), and possibly the degree distributions of the graph, to estimate the error floor.The proposed techniques in this thesis fit within the second category.The linear state-space model is a well-known code-independent method to estimate the contribution of a trapping set structure to the error floor of low-density paritycheck codes.In this thesis we first provide an in-depth analysis of this method by incorporating a more accurate model for the incoming messages to the TS structure that takes into account the randomness and the correlation among such messages.Based on this analysis, we demonstrate that both randomness and correlation result in the over-estimation of the failure probability of the TS.We then propose an alternate code-independent technique for the error floor estimation of iterative LDPC decoders that can accurately estimate the contribution of different TS structures in the error floor.Compared to the linear state-space model, the proposed method is not only more accurate, but also more general, in that, it is applicable to any saturating iterative message-passing decoder, symmetrically quantized or unquantized, over any memoryless binary-input output-symmetric channel.To the best of our knowledge, all the existing work on the theoretical analysis of error floor is limited to two-phase message passing algorithms, also known as flooding or parallel schedule.There are however a variety of message passing schedules which iii 4.5 The steps of constructing the digraph D l (S) of the (5, 3) LETS for a layered decoder from the flooding digraph D f (S).(The colors (edge types) red (dotted), blue (dashed) and purple (dash-dotted) represent L 1 , L 2 and L 3 , respectively.) . . . . . . . . . . . . . . . . . . . . . .69 4.6 QC-LDPC codes used for simulations.The entries of the matrices, that are not equal to -1, represent the right circular shift of the identity matrix to create the corresponding block of the parity-check matrix.The -1 entries represent zero blocks. . . . . . . . . . . . . . . . . . .80 4.7 Simulation and estimation results of C 1 for different saturation levels.The maximum number of iterations I max = 30. . . . . . . . . . . . .81 4.8 The (5, 5) LETS structure of C 1 in which the row layers for different CNs are shown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 4.9 The approximate estimate of the failure probability of the (5, 5) LETS of C 1 for various row layered schedules at E b /N 0 = 6 dB and saturation level 31.75.The schedules are sorted based on r. . . . . . . . . . . .83 4.10 The simulation and estimation results of C 1 for different row schedules.(The saturation level is 31.75, and the maximum number of iterations for layered schedules and the flooding schedule are set to 30 and 60, respectively.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 4.11 The effect of various row layered schedules on the failure probability of different classes of LETSs in C 2 (E b /N 0 = 6 dB, saturation level 15.75).85 4.12 The effect of various row layered schedules on the total FER of C 2 (E b /N 0 = 6 dB, saturation level 15.75). . . . . . . . . . . . . . . . . .85 4.13 The error estimation of the ten (7, 1) LETS groups of C 2 for the two schedules (1, 2, 3, 4, 5, 6) and (4, 1, 5, 2, 3, 6) (saturation level 15.75). .86 4.14 Simulation and estimation results of C 2 for the two schedules (1, 2, 3, 4, 5, 6) and (4, 1, 5, 2, 3, 6) (saturation level 15.75,I max = 30). .87 5.1 A labelled (5,3) LETS of the Tanner (155, 64) code in which the flow of the state variables are shown.The VNs, mis-satisfied CNs and unsatisfied CNs are shown by black circles, white squares and gray squares, respectively.The directed edges related to the layers number 1, 2 and 3 are represented by red, blue and purple colors, respectively.93 xiii 5.2 The VNs v 1 and v 4 related to Fig. 5.1 with the mis-satisfied CN c j connecting them.Figures (a) and (b) are related to virtual VNs, v k and v k , that are used during the update of VNs from layers L 1 and L 3 , respectively.. . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 5.3 Base graph of Example 16: The solid (red), dashed (green), dotted (blue) and dashed-dotted (purple) arrows, respectively, illustrate the updating order which the column layered decoder perform, accordingly.109 5.4 The error estimation related to (5, 5) LETS of C 1 for various column layered schedules at E b /N 0 = 6 dB.All the schedules result in the same dominant eigenvalue of the layered transition matrix, r = 16.9536.The saturation level is 15.75. . . . . . . . . . . . . . . . . . . . . . . . . .111 5.5 The simulation and estimation results related to code C 1 showing the effect of different schedules.The saturation level is 15.75 and the maximum number of iterations is 30. . . . . . . . . . . . . . . . . . .111 5.6 The simulation and estimation results related to code C 2 showing the effect of different schedules.The saturation level is 15.75.The maximum number of iterations is 30. . . . . . . . . . . . . . . . . . . . .113 6.1 The histogram of the conditional error indicator function of a (5, 5) ETS of (640, 192) QC-LDPC code [3] at different iterations. . . . . .128 6.2 Simulation and estimation results for C 1 decoded by SPA over the AWGN channel (I max = 200). . . . . . . . . . . . . . . . . . . . . . .134 6.3 Simulation and extrapolated estimation results for C 1 decoded by SPA over the AWGN channel (I max = 200).The extrapolated curves are obtained based on the results at E b /N 0 = 4.5 dB . . . . . . . . . . . .136 6.4 Simulation and estimation results for C 2 decoded by SPA over the AWGN channel (I max = 200, C th = 25).The extrapolation in DSLM E is based on the results at E b /N 0 = 2.75 dB. . . . . . . . . . . . . . . .136 6.5 Simulation and estimation results for C 3 decoded by SPA over the AWGN channel (I max = 200).The extrapolation in DSLM E is based on the results at E b /N 0 = 4.5 dB. . . . . . . .
Error correcting codes are used in virtually all communication systems to ensure reliable transmission of information. In 1948, Shannon established an upper-bound on the maximum rate at which information can be transmitted reliably over a noisy channel. Reliably transmitting information with a rate close to this theoretical limit, known as the channel capacity, has been the goal of channel coding scientists for the last five decades. The rediscovery of low-density parity-check (LDPC) codes in the 1990s added much-renewed excitement in the coding community. LDPC codes are interesting because they can approach channel capacity under sub-optimum decoding algorithms whose complexity is linear in the code length. Unsurprisingly, LDPC codes quickly attained their popularity in practical applications such as magnetic storage, wireless and optical communications. One, if not the most, important and challenging problem in LDPC code research is the study and analysis of the error floor phenomenon. This phenomenon is described as an abrupt degradation in the frame error rate performance of LDPC codes in the high signal-to-noise ratio region. Error floor is harmful because its presence prevents the LDPC decoder from reaching very low probability of decoding failure, an important requirement for many applications. Not long after the rediscovery of LDPC codes, scientists established that error floor is caused by certain harmful structures, most commonly known as trapping sets, in the Tanner representation of a code. Since then, the study of error floor mostly consists of three major problems: 1) estimating error floor; 2) constructing LDPC codes with low error floor and 3) designing decoders that are less susceptible to error floor. Although some parts of this dissertation can be used as important elements in error floor estimation, our main contributions are a novel method for constructing LDPC codes with low error floor and a novel class of low complexity decoding algorithms that can collectively alleviate error floor. These contributions are summarized as follows. A method to construct LDPC codes with low error floors on the binary symmetric channel is presented. Codes are constructed so that their Tanner graphs are free of certain small trapping sets. These trapping sets are selected from the Trapping Set Ontology for the Gallager A/B decoder. They are selected based on their relative harmfulness for a given decoding algorithm. We evaluate the relative harmfulness of different trapping sets for the sum-product algorithm by using the topological relations among them and by analyzing the decoding failures on one trapping set in the presence or absence of other trapping sets. We apply this method to construct structured LDPC codes. To facilitate the discussion, we give a new description of structured LDPC codes whose parity-check matrices are arrays of permutation matrices. This description uses Latin squares to define a set of permutation matrices that have disjoint support and to derive a simple necessary and sufficient condition for the Tanner graph of a code to be free of four-cycles. A new class of bit flipping algorithms for LDPC codes over the binary symmetric channel is proposed. Compared to the regular (parallel or serial) bit flipping algorithms, the proposed algorithms employ one additional bit at a variable node to represent its "strength." The introduction of this additional bit allows an increase in the guaranteed error correction capability. An additional bit is also employed at a check node to capture information which is beneficial to decoding. A framework for failure analysis and selection of two-bit bit flipping algorithms is provided. The main component of this framework is the (re)definition of trapping sets, which are the most "compact" Tanner graphs that cause decoding failures of an algorithm. A recursive procedure to enumerate trapping sets is described. This procedure is the basis for selecting a collection of algorithms that work well together. It is demonstrated that decoders which employ a properly selected group of the proposed algorithms operating in parallel can offer high speed and low error floor decoding.
The performance of low-density parity-check (LDPC) codes at high signal-to- noise ratios (SNRs) is known to be limited by the presence of certain sub-graphs that exist in the Tanner graph representation of the code, for example trapping sets and absorbing sets. This dissertation derives a lower bound on the frame error rate (FER) of any LDPC code containing a given problematic sub-graph, assuming a particular iterative message passing (MP) decoder and decoder quantization. A crucial aspect of the lower bound is that it is code-independent, in the sense that it can be derived based only on a problematic sub-graph and then applied to any code containing it. Due to the complexity of evaluating the exact bound, assumptions are proposed to approximate it, from which we can estimate decoder performance. For LDPC codes, the attenuated min-sum algorithm (AMSA) and the offset min- sum algorithm (OMSA) are known to outperform the conventional min-sum algorithm (MSA) at low SNRs, i.e., in the waterfall region of the FER curve. This dis- sertation demonstrates that, for quantized LDPC decoders, the AMSA and OMSA underperform the MSA at high SNRs, i.e., in the error floor region of the FER curve, and that the MSA, AMSA, and OMSA all suffer from a relatively high error floor. Therefore, we introduce a novel modification of the MSA for quantized decoding of LDPC codes, called the threshold attenuated min-sum algorithm (TAMSA) (or the threshold offset min-sum algorithm (TOMSA)) with the aim of outperforming the MSA, AMSA, and OMSA at both low and high SNRs. The new decoding algorithm is designed based on the common assumption that trapping sets are the major cause of the error floor for quantized LDPC decoders, and it is shown to reduce the error probability associated with these problematic graphic objects. The lower bound analysis tool noted above is then used to verify the effectiveness of the new TAMSA (TOMSA) and also to assist in finding its optimum design parameters. We also show that the implementation complexity of the TAMSA (TOMSA) is only slightly higher than that of the AMSA or OMSA. Finally, we extend the lower bound to sliding window (SW) decoding of spatially coupled LDPC (SC-LDPC) codes. Additionally, we show that the performance of the TAMSA (TOMSA) is better than that of the MSA, AMSA, and OMSA for SW.