The probability models of 2 different quantum cellular automaton (QCA) adders are based on the theory of probabilistic transfer matrix and circuit partition. The effect of individual component on the overall fault-tolerance is fully analyzed at the same level. The simulation shows that the effect of the wire is minor when the success probability is low, while the overall fault-tolerance rises sharply once the success probability is high. And the inverter is considered to be a major factor that affects the overall fault-tolerance in the variation range of parameter. Frobenbius norm of the overall error probabilistic transfer matrix is employed to study the fault-tolerance difference. The result shows that the overall fault-tolerance of QCA adder consisting of 5-input majority is superior to the other. Such fault-tolerance analyses should be used for a better characterization of QCA circuit design and fault-tolerance improvement.
The probability models of 2 different quantum cellular automaton (QCA) adders are based on the theory of probabilistic transfer matrix and circuit partition. The effect of individual component on the overall fault-tolerance is fully analyzed at the same level. The simulation shows that the effect of the wire is minor when the success probability is low, while the overall fault-tolerance rises sharply once the success probability is high. And the inverter is considered to be a major factor that affects the overall fault-tolerance in the variation range of parameter. Frobenbius norm of the overall error probabilistic transfer matrix is employed to study the fault-tolerance difference. The result shows that the overall fault-tolerance of QCA adder consisting of 5-input majority is superior to the other. Such fault-tolerance analyses should be used for a better characterization of QCA circuit design and fault-tolerance improvement.
We present a numerical study of fault tolerance properties in quantum-dot cellular automata (QCA) devices. A full-basis quantum method is used for calculations of the Hamiltonian, and a statistical model has been introduced to simulate the influence of position defects of the dots within cells on the logical output. Combined effects of temperature and cell defects on a shift register have been studied. Uniform and normal distributions have been used for the cell defect simulations. Normal distribution simulations produce realistic results compared to the uniform distribution. In order to show the operational limit of a device, parameters such as “displacement factor” and “success rate” are introduced. Results show that the fault tolerance of a QCA device is strongly dependent on temperature as well as on the cell defects. The robustness of a shift register is also dependent on the size of the device.
A quantum cellular automaton (QCA) is a unitary discrete-time evolution of a quantum many-body system, which can be described as a dynamics system , where A is any matrix and is a unitary operator representing the global evolution of QCA. And QCAs are characterized by locality (or causality). Among them, quantum circuits are the special classes of QCAs, which use unitary operators to control and transform the initial quantum state of qubit into a final quantum state, quantum circuits are special and widely studied in quantum information. A group is a set of elements combined with an operation, which satisfies associativity, identity and invertibility. This article shows that group theory provides the right language for studying the relation between QCAs and quantum circuits among them.
Quantum computing performance simulators are needed to provide practical metrics for the effectiveness of executing theoretical quantum information processing protocols on physical hardware. In this work, we present a tool to simulate the execution of fault-tolerant quantum computation by automating the tracking of common fault paths for error propagation through an encoded circuit block and quantifying the failure probability of each encoded qubit throughout the circuit. Our simulator runs a fault path counter on encoded circuit blocks to determine the probability that two or more errors remain on the encoded qubits after each block is executed, and it combines errors from all the encoded blocks to estimate performance metrics such as the logical qubit failure probability, the overall circuit failure probability, the number of qubits used, and the time required to run the overall circuit. Our technique efficiently estimates the upper bound of the error probability and provides a useful measure of the error threshold at low error probabilities where conventional Monte Carlo methods are ineffective. We describe a way of simplifying the fault-tolerant measurement process in the Steane code to reduce the number of error correction steps necessary. We present simulation results comparing the execution of quantum adders, which constitute a major part of Shor’s algorithm.
The design of arithmetic and logical unit is a crucial block schematic of quantum computing, which has gained popularity in recent years. While division is a successive subtraction, a logical multiplier employs the technique of successive addition, which are the essential blocks of the quantum computing. The key components including comparator design, adders, and subtractors are considered with the help of Quantum-Dot Cellular Automata (QCA) in this work. Such essential blocks of the Arithmetic Logic Unit (ALU) are designed, implemented, and tested in the simulation using QCADesigner version 2.0.3. The results are found to be appealing with the standard truth tables of the above logical circuits. Hence, the designs could be utilized in the practical applications of Internet of Things, Block chains and Cryptographic solutions catering to the challenges of industry, healthcare and finance sectors. Addressing challenges such as a reduced number of qubits and complexity reduction could make way for more robust and practical ALU designs in QCA-based quantum systems. In the proposed novel work, the number of qubits required has been reduced to 24, offering a notable reduction compared to several recent approaches. Hence, the novelty of the work lies in the architectural-level reorganization and logic-level minimization strategy, which collectively enable a significant reduction in design complexity (up to 93%) without introducing additional fabrication or simulation overhead, optimizing clock zone assignments to enhance timing efficiency.
Quantum computing is gaining importance as a promising approach for achieving energy-efficient and reliable computation, where reversible logic circuits play a key role. Full adders are fundamental components of arithmetic and logic units, and their correct operation is essential for overall system performance. With continued technology scaling, digital circuits are increasingly affected by manufacturing defects and permanent faults, making fault modeling and testability analysis critically important. Among various fault models, the stuck-at fault model is widely used due to its simplicity and its ability to represent common physical defects. This paper presents a detailed stuck-at fault analysis of a reversible full adder designed using Peres gates. The proposed architecture efficiently generates Sum and Carry outputs while reducing gate count and information loss. To evaluate practical feasibility, the full adder is implemented on the IBM quantum computing platform using IBM Composer and simulated through the Qiskit framework. Both fault-free and faulty conditions are examined by introducing stuck- at-0 and stuck-at-1 faults at key nodes affecting the Sum and Carry outputs. State-vector analysis, probability distributions, and measurement results are obtained for all possible input combinations. The exhaustive fault analysis achieves a fault coverage of 87.5% for both SA-0 and SA-1 conditions, indicating high fault observability. The results confirm that the proposed Peres gate–based reversible full adder is well suited for fault-tolerant arithmetic applications in reversible and quantum computing environments.
We extend standard fault tolerance theory and Kitaev’s model for quantum computation so as to enable quantitative determination of design parameters for quantum computers that ensure that the overall computation yields a correct final result with some prescribed probability, as opposed to merely ensuring that the desired final quantum state is obtained. Our extension allows us to explicitly calculate the number of levels of error correction concatenation needed to achieve a correct final result with some prescribed success probability and demonstrate a clear connection between error correction and fault tolerance.