Quantum computing performance simulators are needed to provide practical metrics for the effectiveness of executing theoretical quantum information processing protocols on physical hardware. In this work, we present a tool to simulate the execution of fault-tolerant quantum computation by automating the tracking of common fault paths for error propagation through an encoded circuit block and quantifying the failure probability of each encoded qubit throughout the circuit. Our simulator runs a fault path counter on encoded circuit blocks to determine the probability that two or more errors remain on the encoded qubits after each block is executed, and it combines errors from all the encoded blocks to estimate performance metrics such as the logical qubit failure probability, the overall circuit failure probability, the number of qubits used, and the time required to run the overall circuit. Our technique efficiently estimates the upper bound of the error probability and provides a useful measure of the error threshold at low error probabilities where conventional Monte Carlo methods are ineffective. We describe a way of simplifying the fault-tolerant measurement process in the Steane code to reduce the number of error correction steps necessary. We present simulation results comparing the execution of quantum adders, which constitute a major part of Shor’s algorithm.
Quantum computing performance simulators are needed to provide practical metrics for the effectiveness of executing theoretical quantum information processing protocols on physical hardware. In this work, we present a tool to simulate the execution of fault-tolerant quantum computation by automating the tracking of common fault paths for error propagation through an encoded circuit block and quantifying the failure probability of each encoded qubit throughout the circuit. Our simulator runs a fault path counter on encoded circuit blocks to determine the probability that two or more errors remain on the encoded qubits after each block is executed, and it combines errors from all the encoded blocks to estimate performance metrics such as the logical qubit failure probability, the overall circuit failure probability, the number of qubits used, and the time required to run the overall circuit. Our technique efficiently estimates the upper bound of the error probability and provides a useful measure of the error threshold at low error probabilities where conventional Monte Carlo methods are ineffective. We describe a way of simplifying the fault-tolerant measurement process in the Steane code to reduce the number of error correction steps necessary. We present simulation results comparing the execution of quantum adders, which constitute a major part of Shor’s algorithm.
Quantum performance simulators can provide practical metrics for the effectiveness of executing theoretical quantum information processing protocols on physical hardware. In this work we present a scheme to simulate the performance of fault tolerant quantum computation by automating the tracking of common fault paths for error propagation through a circuit and quantifying the fidelity of each qubit throughout the computation. Our simulation tool outputs the expected execution time, required number of qubits and the final error rate of running common fault tolerant protocols on a universal hardware, assumed to be a network of qubits with full connectivity. Our technique efficiently estimates the upper bound of error probability and provides a useful performance measure of the error threshold at low error rates where conventional Monte Carlo methods are ineffective. To verify the proposed simulator, we present simulation results comparing the execution of quantum adders which constitute a major part of Shor's algorithm.
Due to very high projected error rates, large scale quantum computers will require substantial fault tolerance just to maintain a minimum level of reliability. We present tools to better analyze the performance of large, fault tolerant quantum computer designs. We find that current uses of quantum error correction are overly conservative in mitigating the impact of gate errors and negligent of other error sources in quantum data communication and memory.
We have developed circuit layout heuristics to generate detailed designs in trapped ion quantum computing technology. From these designs, we can extract much more accurate error models for a given application, including all gate, movement and idle errors on qubits. Using these extracted models, our flexible error simulation environment determines the overall failure probability of the design. Included in this simulation environment is a bit-parallel Monte Carlo technique that is 10 times faster than previous fault propagation simulations. This allows us to evaluate the reliability of designs that are an order of magnitude larger, in the same amount of time.
Using this analysis framework to verify reliability, we have developed a linear programming-based optimization for error correction which decreases overall circuit resources by an order of magnitude. In some cases, our optimization actually improves overall system reliability by removing error correction. We combine this optimization with judicious quantum error correcting code selection to provide efficient designs for large quantum arithmetic kernels used in Shor's factorization algorithm. We show our optimized designs perform 2x to 100x better than previous works in terms of probabilistic area-delay product. Additionally, the area of our layout of a 1024-bit factoring using Shor's algorithm is 64cm2, a substantial improvement compared to the 0.9m2 state-of-the-art design from prior work. A design size reduction by this amount will make fabricating such an application feasible much sooner.
The optimal design of a fault-tolerant quantum computer involves finding an appropriate balance between the burden of large-scale integration of noisy components and the load of improving the reliability of hardware technology. This balance can be evaluated by quantitatively modeling the execution of quantum logic operations on a realistic quantum hardware containing limited computational resources. In this work, we report a complete performance simulation software tool capable of (1) searching the hardware design space by varying resource architecture and technology parameters, (2) synthesizing and scheduling a fault-tolerant quantum algorithm within the hardware constraints, (3) quantifying the performance metrics such as the execution time and the failure probability of the algorithm, and (4) analyzing the breakdown of these metrics to highlight the performance bottlenecks and visualizing resource utilization to evaluate the adequacy of the chosen design. Using this tool, we investigate a vast design space for implementing key building blocks of Shor’s algorithm to factor a 1,024-bit number with a baseline budget of 1.5 million qubits. We show that a trapped-ion quantum computer designed with twice as many qubits and one-tenth of the baseline infidelity of the communication channel can factor a 2,048-bit integer in less than 5 months.
Scaling up quantum algorithms to tackle high-impact problems in science and industry requires quantum error correction and fault tolerance. While progress has been made in experimentally realizing error-corrected primitives, the end-to-end execution of logical quantum algorithms using only fault-tolerant (FT) components has remained out of reach. We demonstrate the FT and error-corrected execution of two quantum algorithms, the Quantum Approximate Optimization Algorithm (QAOA) and the Harrow-Hassidim-Lloyd (HHL) algorithm applied to the Poisson equation, on Quantinuum H2 and Helios trapped-ion quantum processors using the [[7,1,3]] Steane code. For QAOA circuits on 5 and 6 logical qubits, we show performance improvements from increasing the number of QAOA layers and the number of T gates used to approximate logical rotations, despite increased physical circuit complexity. We further show that QAOA circuits with up to 8 logical qubits and 9 logical T gates perform similarly to unencoded circuits. For the largest QAOA circuits we run, with 12 logical (97 physical) qubits and 2132 physical two-qubit gates, we still observe better-than-random performance. Finally, we show that adding active QEC cycles and increasing the repeat-until-success limit of state preparation subroutines can improve the performance of a quantum algorithm, thereby demonstrating critical capabilities of scalable FT quantum computation. Our results are enabled by an FT logical T gate implementation with an infidelity of ∼2.6(4)×10−3 and dynamic circuits with measurement-dependent feedback. Our work demonstrates near-break-even performance of complex, error-corrected algorithmic quantum circuits using only FT components.
Quantum computers promise to solve computational problems that are inaccessible to classical machines. The reliable execution of large-scale quantum algorithms requires robust operations in the presence of noise. Quantum error correction addresses this challenge by encoding quantum information redundantly across several physical qubits, such that errors can be detected and corrected during a computation. However, no single error-correcting code intrinsically supports an inherently robust, fault-tolerant implementation of all gates needed for universal quantum computing. Moreover, most modern approaches to both quantum error correction and the implementation of universal logical operations on encoded qubits rely on mid-circuit measurements and feed-forward control. These types of operations are technologically demanding, often slow, and prone to high error rates, and they limit the overall success probability of quantum algorithms. In this thesis, we develop fault-tolerant protocols and circuits for quantum error correction and universal logical computation, with an emphasis on implementations compatible with current hardware systems. We first focus on fault-tolerant quantum error correction on small codes. By comparing different protocols, we identify trade-offs between compact circuit constructions and their robustness to noise. We then assess their practical performance by comparing numerical simulations of noisy circuits with experimental data. Beyond the preservation of encoded information, we study how universal logic can be implemented in a fault-tolerant manner on encoded qubits. A central approach considered in this thesis is code switching, in which logical information is transferred between two distinct error-correcting codes that support complementary sets of inherently fault-tolerant logical gates. In combination, these codes give access to a complete universal fault-tolerant logical gate set. In this thesis, we determine conditions that allow us to construct fault-tolerant protocols for code switching. We adapt these protocols to the capabilities of current hardware, thereby enabling the first experimental realization of universal fault-tolerant logic by means of code switching. However, the overall performance of these schemes is limited by slow and noisy mid-circuit measurements. To address this bottleneck, we construct a suite of measurement-free fault-tolerant universal operations that do not require any measurements during the execution of an algorithm. In this framework, error correction and logical operations are implemented coherently as part of the quantum circuit, without mid-circuit measurements or in-sequence classical control. We introduce measurement-free code-switching schemes that can be scaled to arbitrary code distances through concatenation, and which thereby provide, in principle, arbitrarily strong error suppression. We further tailor our approach to the capabilities of current trapped-ion quantum processors. New circuit constructions support the first experimental implementation of a logical quantum algorithm without mid-circuit measurements, demonstrated through Grover's search on three encoded qubits. Together, the results of this thesis expand the toolbox for early fault-tolerant quantum computation. They show how protocols for quantum error correction and universal logical gates can be designed without mid-circuit measurements with realistic hardware constraints in mind, opening new pathways towards universal quantum logic.
Quantum computation holds the promise of solving certain complex problems exponentially faster than classical computers. However, the high prevalent noise in current quantum devices impedes the accurate execution of even basic algorithms. This can be remedied by protecting quantum information with a quantum error-correcting code, where the logical information of an algorithmic qubit is spread across multiple physical qubits. Individual quantum errors are then located and corrected by the fault-tolerant measurement of multi-qubit stabilizer operators (parity checks). Unfortunately, error correction and fault tolerance both impose large demands on the qubit overhead: hundreds to thousands of physical qubits per logical qubit.
We reduce the spacetime cost of fault tolerance by redesigning key building blocks of an error-corrected quantum computer. First, we develop a combinatorial proof with flag fault tolerance that exponentially reduces the extra qubits needed to measure a stabilizer of any size, while tolerating one fault. We leverage these proofs to then design state preparation circuits for the Steane and Golay codes with 100% yield. Next, we improve error correction on a planar layout by showing that a distance-four code encoding six logical qubits protects information as well as the distance-five surface code, using one-tenth as many physical qubits. Finally, we optimize the time overhead of logical gates in surface code quantum computers by protecting measurement results with a classical code, cutting computation time by a factor of two to six. Our hardware-agnostic optimizations of fault tolerance overheads thus suggest new routes to advance the timeline of error-free quantum computing.