Due to very high projected error rates, large scale quantum computers will require substantial fault tolerance just to maintain a minimum level of reliability. We present tools to better analyze the performance of large, fault tolerant quantum computer designs. We find that current uses of quantum error correction are overly conservative in mitigating the impact of gate errors and negligent of other error sources in quantum data communication and memory.
We have developed circuit layout heuristics to generate detailed designs in trapped ion quantum computing technology. From these designs, we can extract much more accurate error models for a given application, including all gate, movement and idle errors on qubits. Using these extracted models, our flexible error simulation environment determines the overall failure probability of the design. Included in this simulation environment is a bit-parallel Monte Carlo technique that is 10 times faster than previous fault propagation simulations. This allows us to evaluate the reliability of designs that are an order of magnitude larger, in the same amount of time.
Using this analysis framework to verify reliability, we have developed a linear programming-based optimization for error correction which decreases overall circuit resources by an order of magnitude. In some cases, our optimization actually improves overall system reliability by removing error correction. We combine this optimization with judicious quantum error correcting code selection to provide efficient designs for large quantum arithmetic kernels used in Shor's factorization algorithm. We show our optimized designs perform 2x to 100x better than previous works in terms of probabilistic area-delay product. Additionally, the area of our layout of a 1024-bit factoring using Shor's algorithm is 64cm2, a substantial improvement compared to the 0.9m2 state-of-the-art design from prior work. A design size reduction by this amount will make fabricating such an application feasible much sooner.
Due to very high projected error rates, large scale quantum computers will require substantial fault tolerance just to maintain a minimum level of reliability. We present tools to better analyze the performance of large, fault tolerant quantum computer designs. We find that current uses of quantum error correction are overly conservative in mitigating the impact of gate errors and negligent of other error sources in quantum data communication and memory.
We have developed circuit layout heuristics to generate detailed designs in trapped ion quantum computing technology. From these designs, we can extract much more accurate error models for a given application, including all gate, movement and idle errors on qubits. Using these extracted models, our flexible error simulation environment determines the overall failure probability of the design. Included in this simulation environment is a bit-parallel Monte Carlo technique that is 10 times faster than previous fault propagation simulations. This allows us to evaluate the reliability of designs that are an order of magnitude larger, in the same amount of time.
Using this analysis framework to verify reliability, we have developed a linear programming-based optimization for error correction which decreases overall circuit resources by an order of magnitude. In some cases, our optimization actually improves overall system reliability by removing error correction. We combine this optimization with judicious quantum error correcting code selection to provide efficient designs for large quantum arithmetic kernels used in Shor's factorization algorithm. We show our optimized designs perform 2x to 100x better than previous works in terms of probabilistic area-delay product. Additionally, the area of our layout of a 1024-bit factoring using Shor's algorithm is 64cm2, a substantial improvement compared to the 0.9m2 state-of-the-art design from prior work. A design size reduction by this amount will make fabricating such an application feasible much sooner.
The optimal design of a fault-tolerant quantum computer involves finding an appropriate balance between the burden of large-scale integration of noisy components and the load of improving the reliability of hardware technology. This balance can be evaluated by quantitatively modeling the execution of quantum logic operations on a realistic quantum hardware containing limited computational resources. In this work, we report a complete performance simulation software tool capable of (1) searching the hardware design space by varying resource architecture and technology parameters, (2) synthesizing and scheduling a fault-tolerant quantum algorithm within the hardware constraints, (3) quantifying the performance metrics such as the execution time and the failure probability of the algorithm, and (4) analyzing the breakdown of these metrics to highlight the performance bottlenecks and visualizing resource utilization to evaluate the adequacy of the chosen design. Using this tool, we investigate a vast design space for implementing key building blocks of Shor’s algorithm to factor a 1,024-bit number with a baseline budget of 1.5 million qubits. We show that a trapped-ion quantum computer designed with twice as many qubits and one-tenth of the baseline infidelity of the communication channel can factor a 2,048-bit integer in less than 5 months.
Quantum computing performance simulators are needed to provide practical metrics for the effectiveness of executing theoretical quantum information processing protocols on physical hardware. In this work, we present a tool to simulate the execution of fault-tolerant quantum computation by automating the tracking of common fault paths for error propagation through an encoded circuit block and quantifying the failure probability of each encoded qubit throughout the circuit. Our simulator runs a fault path counter on encoded circuit blocks to determine the probability that two or more errors remain on the encoded qubits after each block is executed, and it combines errors from all the encoded blocks to estimate performance metrics such as the logical qubit failure probability, the overall circuit failure probability, the number of qubits used, and the time required to run the overall circuit. Our technique efficiently estimates the upper bound of the error probability and provides a useful measure of the error threshold at low error probabilities where conventional Monte Carlo methods are ineffective. We describe a way of simplifying the fault-tolerant measurement process in the Steane code to reduce the number of error correction steps necessary. We present simulation results comparing the execution of quantum adders, which constitute a major part of Shor’s algorithm.
Quantum error mitigation (QEM) is typically viewed as a suite of practical techniques for today's noisy intermediate-scale quantum devices, with limited relevance once fault-tolerant quantum computers become available. In this work, we challenge this conventional wisdom by showing that QEM can continue to provide substantial benefits in the era of quantum error correction (QEC), and in an even more efficient manner than it does on current devices. We introduce a framework for logical-level QEM that leverages soft information naturally produced by QEC decoders, requiring no additional data, hardware modifications, or runtime overhead beyond what QEC protocols already provide. Within this framework, we develop and analyze three logical-level QEM techniques: post-selection and runtime abort policies, probabilistic error cancellation, and zero-noise extrapolation. Our techniques reduce logical error rates by more than 100x while discarding fewer than 0.1% of shots; they also provide in situ characterization of logical channels for QEM protocols. As a proof of principle, we benchmark our approach using a surface-code architecture and two state-of-the-art decoders based on tensor-network contraction and minimum-weight perfect matching. We evaluate logical-level QEM on random Clifford circuits and molecular simulation algorithms and find that, compared to previous approaches relying on QEC only or QEC combined with QEM, we can achieve up to 87.4% spacetime overhead savings. Our results demonstrate that logical-level QEM with QEC decoder soft information can reliably improve logical performance, underscoring the efficiency and usefulness of QEM techniques for fault-tolerant quantum computers.
Quantum error correction protects fragile quantum information by encoding it into a larger quantum system. These extra degrees of freedom enable the detection and correction of errors, but also increase the operational complexity of the encoded logical qubit. Fault-tolerant circuits contain the spread of errors while operating the logical qubit, and are essential for realizing error suppression in practice. While fault-tolerant design works in principle, it has not previously been demonstrated in an error-corrected physical system with native noise characteristics. In this work, we experimentally demonstrate fault-tolerant preparation, measurement, rotation, and stabilizer measurement of a Bacon-Shor logical qubit using 13 trapped ion qubits. When we compare these fault-tolerant protocols to non-fault tolerant protocols, we see significant reductions in the error rates of the logical primitives in the presence of noise. The result of fault-tolerant design is an average state preparation and measurement error of 0.6% and a Clifford gate error of 0.3% after error correction. Additionally, we prepare magic states with fidelities exceeding the distillation threshold, demonstrating all of the key single-qubit ingredients required for universal fault-tolerant operation. These results demonstrate that fault-tolerant circuits enable highly accurate logical primitives in current quantum systems. With improved two-qubit gates and the use of intermediate measurements, a stabilized logical qubit can be achieved.
Quantum error correction (QEC) represents the cornerstone technology for realizing fault-tolerant quantum computing, addressing the fundamental challenge of quantum state decoherence in noisy intermediate-scale quantum (NISQ) devices. This comprehensive review examines recent advances in QEC implementations from 2020-2024, spanning theoretical foundations to practical hardware demonstrations. We analyze the evolution from pioneering stabilizer codes to modern topological approaches, with particular emphasis on surface codes and low-density parity-check (LDPC) codes that have demonstrated below-threshold error correction in superconducting and trapped-ion systems. The paper provides a comparative analysis of classical and machine learning-based decoder algorithms, evaluating their performance through complexity analysis and threshold comparisons in real-time error correction scenarios. Through examination of breakthrough experiments by Google, IBM, Quantinuum, and emerging platforms, we assess the current state of fault-tolerant quantum computing and identify critical engineering challenges including correlated noise models, cryogenic control systems, and scalable logical gate implementations. Our quantitative analysis reveals that while significant progress has been made toward practical fault-tolerance thresholds, achieving the resource efficiency and reliability required for large-scale quantum computation remains challenging. We provide detailed resource estimates for key applications including Shor's algorithm and optimization problems, along with analysis of industry roadmaps toward thousand-logical-qubit systems. This review serves as a comprehensive guide for researchers and engineers working toward the next generation of fault-tolerant quantum computers, with particular focus on information-theoretic perspectives relevant to quantum information entropy and syndrome processing.
Quantum error correction (QEC) represents the cornerstone technology for realizing fault-tolerant quantum computing, addressing the fundamental challenge of quantum state decoherence in noisy intermediate-scale quantum (NISQ) devices. This comprehensive review examines recent advances in QEC implementations from 2020-2024, spanning theoretical foundations to practical hardware demonstrations. We analyze the evolution from pioneering stabilizer codes to modern topological approaches, with particular emphasis on surface codes and low-density parity-check (LDPC) codes that have demonstrated below-threshold error correction in superconducting and trapped-ion systems. The paper provides a comparative analysis of classical and machine learning-based decoder algorithms, evaluating their performance through complexity analysis and threshold comparisons in real-time error correction scenarios. Through examination of breakthrough experiments by Google, IBM, Quantinuum, and emerging platforms, we assess the current state of fault-tolerant quantum computing and identify critical engineering challenges including correlated noise models, cryogenic control systems, and scalable logical gate implementations. Our quantitative analysis reveals that while significant progress has been made toward practical fault-tolerance thresholds, achieving the resource efficiency and reliability required for large-scale quantum computation remains challenging. We provide detailed resource estimates for key applications including Shor's algorithm and optimization problems, along with analysis of industry roadmaps toward thousand-logical-qubit systems. This review serves as a comprehensive guide for researchers and engineers working toward the next generation of fault-tolerant quantum computers, with particular focus on information-theoretic perspectives relevant to quantum information entropy and syndrome processing.