Quantum computing is gaining importance as a promising approach for achieving energy-efficient and reliable computation, where reversible logic circuits play a key role. Full adders are fundamental components of arithmetic and logic units, and their correct operation is essential for overall system performance. With continued technology scaling, digital circuits are increasingly affected by manufacturing defects and permanent faults, making fault modeling and testability analysis critically important. Among various fault models, the stuck-at fault model is widely used due to its simplicity and its ability to represent common physical defects. This paper presents a detailed stuck-at fault analysis of a reversible full adder designed using Peres gates. The proposed architecture efficiently generates Sum and Carry outputs while reducing gate count and information loss. To evaluate practical feasibility, the full adder is implemented on the IBM quantum computing platform using IBM Composer and simulated through the Qiskit framework. Both fault-free and faulty conditions are examined by introducing stuck- at-0 and stuck-at-1 faults at key nodes affecting the Sum and Carry outputs. State-vector analysis, probability distributions, and measurement results are obtained for all possible input combinations. The exhaustive fault analysis achieves a fault coverage of 87.5% for both SA-0 and SA-1 conditions, indicating high fault observability. The results confirm that the proposed Peres gate–based reversible full adder is well suited for fault-tolerant arithmetic applications in reversible and quantum computing environments.
Quantum computing is gaining importance as a promising approach for achieving energy-efficient and reliable computation, where reversible logic circuits play a key role. Full adders are fundamental components of arithmetic and logic units, and their correct operation is essential for overall system performance. With continued technology scaling, digital circuits are increasingly affected by manufacturing defects and permanent faults, making fault modeling and testability analysis critically important. Among various fault models, the stuck-at fault model is widely used due to its simplicity and its ability to represent common physical defects. This paper presents a detailed stuck-at fault analysis of a reversible full adder designed using Peres gates. The proposed architecture efficiently generates Sum and Carry outputs while reducing gate count and information loss. To evaluate practical feasibility, the full adder is implemented on the IBM quantum computing platform using IBM Composer and simulated through the Qiskit framework. Both fault-free and faulty conditions are examined by introducing stuck- at-0 and stuck-at-1 faults at key nodes affecting the Sum and Carry outputs. State-vector analysis, probability distributions, and measurement results are obtained for all possible input combinations. The exhaustive fault analysis achieves a fault coverage of 87.5% for both SA-0 and SA-1 conditions, indicating high fault observability. The results confirm that the proposed Peres gate–based reversible full adder is well suited for fault-tolerant arithmetic applications in reversible and quantum computing environments.
The performance of existing technology for implementing digital circuits based on irreversible logic is closely reaching its limit. Conventional logic circuits result in heat dissipation whenever there is an information loss. Hence reversible logic is attaining major consideration in the perspective of evolving technologies such as quantum computing as there isno information loss and there is a unique mapping between the input vectors and output vectors. A reversible gate is supposed to be parity preserving if there existsimilarity between input parityand the outputparity.To construct reliable fault-tolerant reversible systems elements should be of fault-tolerant reversiblestructures.Adder circuits are studied extensively since their performance can directly affect the entire digital system. This paper presents a Toffoli gate (TG) based fulladderwhich serves as a fundamental component in constructing a ripple carry adder. Further a parity preserving Toffoligate based full adder is presented which was utilized to develop a fault-tolerant Ripple Carry Adder without compromising on its performance.The proposed designs have been simulated using IBM Quantum Simulator and have been verified for their correctness. The proposed adders will serve as vital design components in developing fault-tolerant reversible arithmetic and logic unit.
Abstract This paper presents a reversible, n‑bit Quantum Arithmetic Logic Unit (QALU) implemented in Qiskit that supports a classical ALU‑like instruction set: ADD, SUB, CMP, AND/OR/XOR and their negations, unary NOT, shifts and rotates, and operand passthrough. The QALU outputs a result register and status flags N, Z, C, V (negative, zero, carry/no‑borrow, signed overflow) and emits explicit comparison outputs EQ, LT u , LT s . The design is modular and operation‑selectable at compile time, enabling clean verification and resource accounting. To evaluate fault‑tolerant efficiency, the circuits are decomposed into a Clifford + T basis and measure T‑count alongside CX‑count and depth. Exhaustive verification on Aer (matrix‑product‑state simulation) confirms correctness for all input pairs for n = 4 across 16 operations. Hardware experiments on IBM Quantum (limited to n = 2) demonstrate end‑to‑end execution with dynamical decoupling and gate twirling, and readout mitigation via mthree. An analytical scaling discussion grounded in ripple‑carry adder theory and known Toffoli/T‑gate constructions is further provided. These results show that a practical, verifiable QALU with flags and compare can be implemented within Qiskit while exposing meaningful fault‑tolerant metrics and hardware‑realistic performance characterization. Key findings from the provided implementation artifacts: (1) Aer exhaustive verification (n = 4): the QALU was exhaustively tested over all 2 2n =256 input pairs for each of 16 operations (4096 total tests), with 0 mismatches against a classical reference model. (2) Resource metrics (n = 4): after transpilation to a Clifford + T‑style basis {cx, h, s, sdg, x, z, t, tdg} at optimization level 3, the highest‑cost operations (ADD, SUB, CMP) report T‑count = 86, CX‑count ≈ 102–106, and depth ≈ 138 on a 24‑qubit circuit instance (including flags and MCX ancillae). (3) IBM hardware test (n = 2): on an automatically selected IBM backend (ibm_torino) using dynamical decoupling and gate twirling plus mthree readout mitigation, an exhaustive run over all 256 circuits yielded raw correctness 91.41% and mitigated correctness 91.02% (slightly worse post‑mitigation, consistent with practical tradeoffs where mitigation noise/calibration drift can dominate at small sizes).
Reversible logic is characterized by its feature of being a prominent application in low-power conventional computers and the most compatible logic in quantum computers. Quantum circuits executes quantum algorithms and are important in a new generation of advanced computing. However, they are highly error-prone and also subject to the use of limited and sensitive physical resources like qubits and quantum gates. This paper introduces a comprehensive fault tolerant quantum-based reversible circuit which can calculate a high variety number of arithmetic and logic operations. It uses both: parity preserving method for detecting one or an odd number of bit errors, and Clifford + T implementation for protecting circuits against decoherence faults. First, we propose a new fault-tolerant (parity preserving and Clifford + T) adder/subtractor and derive a quantum reversible Arithmetic and Logic Unit (ALU). These modules reach the most optimized extent of circuit line, ancilla inputs, and garbage outputs according to the logical analysis done in this work. This article focuses on reducing T-cost metrics in conjunction with enhancing the number of operations and quantum costs in proposed circuits compared to other counterparts. We propose 4-bit fault tolerant ALU derived from our proposed single-bit module to show the proposed circuit can be extended to any larger size. The proposed circuit is implemented in the Qiskit simulation tool, and output results confirm the accuracy of our design functionality. The proposed full adder/ subtractor achieves an average of 64% and 43%, and the proposed ALU circuit achieves an average of 38% and 27% improvement in T-count and T-depth, respectively compared to their counterparts. The proposed reversible quantum-optimized fault tolerant adder/subtractor and ALU units can be applied as the basic part of DSP systems and quantum processor units in quantum computing devices.
Quantum processors are a central element of a quantum computer. Processors are responsible for performing the fundamental operations like addition, subtraction, etc. of any computer. This also involves the arithmetic unit and has a different configuration for the quantum computer than for a classical computer. Multiplication is essentially repeated addition and division is repeated subtraction. But for quantum computer other methodologies have to be used for arithmetic. In this paper a Quantum Full Adder/Subtractor Circuit, using the reversible Peres Gate, R3Gate and a NOT Gate, is proposed. So, the proposed design can be used for both modes, adder and subtractor on quantum operation. The authors have also compared proposed design with other designs reported, in terms of Gate count, Garbage bits, Quantum cost and Delay. The authors have achieved a 62.5% increment in delay and a low power computing reversible logic in which the computation is faster and energy efficient. Using IBM Qiskit, the authors have created and tested the circuit.
In modern Very-Large-Scale Integration (VLSI) technology, managing information loss is a critical challenge. Conventional logic gates, such as AND, OR, and NOT, are prone to data loss during operations, reducing their efficiency for sophisticated applications. Reversible logic gates, which have an equal number of inputs and outputs, offer a solution by preserving data integrity. This paper presents the design and FPGA implementation of an efficient and high-speed full adder circuit utilizing reversible logic gates, namely Feynman, Toffoli, and Peres gates. The design focuses on improving computational efficiency and thermal performance. An analysis of the circuit's quantum cost, garbage outputs, and ancillary inputs reveals its advantages over traditional designs. Proposed design has been realized using Verilog and Synthesize and simulations performed using Xilinx Vivado and Xilinx ISE tools, confirms the functionality and efficiency of the proposed full adder. FPGA implementation of the design has been done using NEXYS A7 (Artix 7 series). The results show that the circuit has a quantum cost of 10, with two garbage outputs and one ancillary input, underscoring its potential for use in low-power, high-performance computing systems and quantum computing applications.
This paper proposed the design and development of reversible cost-efficient innovative quantum dual-full adder and subtractor or QD-FAS circuit using quantum gate. The proposed circuit can be used as full adder and full subtractor simultaneously, which is designed using double Peres gate or DPG and Feynman gate or FG. The quantum cost, garbage output and constant input of the QD-FAS is 8, 1 and 1. Which is better w.r.t previously reported work. The QD-FAS circuit, as proposed, includes shared sum and difference terminals, as well as a carry-out and a borrow output terminal. Notably, this innovation showcases a remarkable 27.27% reduction in quantum cost. The improvement in garbage output is even more striking, showing a 50% enhancement. When assessing the overall advancement in quantum cost, it falls within the range of 27.27% to 66.66%. To confirm the viability of this design, extensive testing is carried out using the IBM Qiskit simulator. This design holds significant importance in a variety of applications, including quantum computing, cryptography, and the realm of reversible Arithmetic Logic Units (ALU).