The performance of existing technology for implementing digital circuits based on irreversible logic is closely reaching its limit. Conventional logic circuits result in heat dissipation whenever there is an information loss. Hence reversible logic is attaining major consideration in the perspective of evolving technologies such as quantum computing as there isno information loss and there is a unique mapping between the input vectors and output vectors. A reversible gate is supposed to be parity preserving if there existsimilarity between input parityand the outputparity.To construct reliable fault-tolerant reversible systems elements should be of fault-tolerant reversiblestructures.Adder circuits are studied extensively since their performance can directly affect the entire digital system. This paper presents a Toffoli gate (TG) based fulladderwhich serves as a fundamental component in constructing a ripple carry adder. Further a parity preserving Toffoligate based full adder is presented which was utilized to develop a fault-tolerant Ripple Carry Adder without compromising on its performance.The proposed designs have been simulated using IBM Quantum Simulator and have been verified for their correctness. The proposed adders will serve as vital design components in developing fault-tolerant reversible arithmetic and logic unit.
The performance of existing technology for implementing digital circuits based on irreversible logic is closely reaching its limit. Conventional logic circuits result in heat dissipation whenever there is an information loss. Hence reversible logic is attaining major consideration in the perspective of evolving technologies such as quantum computing as there isno information loss and there is a unique mapping between the input vectors and output vectors. A reversible gate is supposed to be parity preserving if there existsimilarity between input parityand the outputparity.To construct reliable fault-tolerant reversible systems elements should be of fault-tolerant reversiblestructures.Adder circuits are studied extensively since their performance can directly affect the entire digital system. This paper presents a Toffoli gate (TG) based fulladderwhich serves as a fundamental component in constructing a ripple carry adder. Further a parity preserving Toffoligate based full adder is presented which was utilized to develop a fault-tolerant Ripple Carry Adder without compromising on its performance.The proposed designs have been simulated using IBM Quantum Simulator and have been verified for their correctness. The proposed adders will serve as vital design components in developing fault-tolerant reversible arithmetic and logic unit.
This paper presents the design, optimization, and simulation of arithmetic circuits using reversible logic for quantum computing applications. The motivation behind this work is to achieve resource-efficient computation through reduced quantum cost, minimized garbage outputs, and lower ancilla requirements. The methodology involves implementing Half Adders, Full Adders, Multiplexers, and Ripple Carry Adders (RCAs) using Toffoli and Peres gates. The proposed 8-bit RCA achieves a quantum cost of 58 using 24 qubits, 8 garbage outputs, and 6 ancilla inputs—showing a significant improvement over conventional Toffoli-based designs that require higher quantum cost and resources. Simulations were conducted on IBM Qiskit and Google Colab using the Qiskit SDK to validate circuit correctness and scalability. The obtained results demonstrate superior resource efficiency and confirm the feasibility of reversible-logic-based quantum arithmetic as a foundation for scalable quantum arithmetic logic units (ALUs) and processors.
Quantum computing is gaining importance as a promising approach for achieving energy-efficient and reliable computation, where reversible logic circuits play a key role. Full adders are fundamental components of arithmetic and logic units, and their correct operation is essential for overall system performance. With continued technology scaling, digital circuits are increasingly affected by manufacturing defects and permanent faults, making fault modeling and testability analysis critically important. Among various fault models, the stuck-at fault model is widely used due to its simplicity and its ability to represent common physical defects. This paper presents a detailed stuck-at fault analysis of a reversible full adder designed using Peres gates. The proposed architecture efficiently generates Sum and Carry outputs while reducing gate count and information loss. To evaluate practical feasibility, the full adder is implemented on the IBM quantum computing platform using IBM Composer and simulated through the Qiskit framework. Both fault-free and faulty conditions are examined by introducing stuck- at-0 and stuck-at-1 faults at key nodes affecting the Sum and Carry outputs. State-vector analysis, probability distributions, and measurement results are obtained for all possible input combinations. The exhaustive fault analysis achieves a fault coverage of 87.5% for both SA-0 and SA-1 conditions, indicating high fault observability. The results confirm that the proposed Peres gate–based reversible full adder is well suited for fault-tolerant arithmetic applications in reversible and quantum computing environments.
A reconfigurable 16-bit adder utilizing reversible logic is introduced to enhance both energy efficiency and computational performance. The design integrates Toffoli, Peres, and Haghparast–Navi Gate (HNG) to construct optimized full adder units with lower quantum cost, reduced garbage outputs, and minimal constant inputs. A reversible multiplexer is employed to enable seamless switching between Ripple Carry Adder (RCA) and Carry Lookahead Adder (CLA) configurations. While RCA mode supports power-efficient operation, CLA mode enables faster computation, allowing the circuit to adapt to different processing requirements. Performance evaluation is carried out considering propagation delay, power consumption and hardware utilization. The analysis indicates enhanced efficiency over existing reversible adder designs. Due to its adaptable structure and scalable nature, the architecture is appropriate for reversible computing, quantum systems, and low-power VLSI applications.
In the context of modern Very Large-Scale Integration (VLSI) technology, information loss has been a major concern. Logic gates (LG) such as AND, OR, and NOT have been found to result in information loss during their operations. To address this issue, reversible LGs have been created. The development and implementation of a high-speed, efficient full adder circuit employing reversible LGs like Feynman, Toffoli, and Peres gates. The design aims to improve computational and thermal efficiencies. The circuit refarding quantum costs (QC), garbage outputs, and ancillary inputs. The implemented the suggested design in Verilog and verified the entire adder's functionality and efficiency through simulations using the Xilinx Vivado and Xilinx ISE tools. The circuit has a quantum cost of 10 with two outputs of useless and one auxiliary input, according to the researchers, highlighting its opportunities for usage in quantum computing applications andlow-power (dec 84%), high-performance computing systems.
Efficient arithmetic operations are a prerequisite for practical quantum computing. Optimization efforts focus on two primary metrics: Quantum Cost (QC), determined by the number of non-linear gates, and Logical Depth, which defines the execution speed. Existing literature identifies the HNG gate as the standard for Input-Preserving Reversible Full Adders. HNG gate typically requires a QC of 12 and a logical depth of 5, in the area of classical reversible circuits. This paper proposes the PPKN Gate, a novel design that achieves the same inputpreserving functionality using only one Toffoli gate and five CNOT gates. With a Quantum Cost of 10 and a reduced logical depth of 4, the PPKN gate outperforms the standard HNG gate in both complexity and speed. Furthermore, we present a modular architecture for constructing an n-bit Ripple Carry Adder by cascading PPKN modules.
Reversible logic is characterized by its feature of being a prominent application in low-power conventional computers and the most compatible logic in quantum computers. Quantum circuits executes quantum algorithms and are important in a new generation of advanced computing. However, they are highly error-prone and also subject to the use of limited and sensitive physical resources like qubits and quantum gates. This paper introduces a comprehensive fault tolerant quantum-based reversible circuit which can calculate a high variety number of arithmetic and logic operations. It uses both: parity preserving method for detecting one or an odd number of bit errors, and Clifford + T implementation for protecting circuits against decoherence faults. First, we propose a new fault-tolerant (parity preserving and Clifford + T) adder/subtractor and derive a quantum reversible Arithmetic and Logic Unit (ALU). These modules reach the most optimized extent of circuit line, ancilla inputs, and garbage outputs according to the logical analysis done in this work. This article focuses on reducing T-cost metrics in conjunction with enhancing the number of operations and quantum costs in proposed circuits compared to other counterparts. We propose 4-bit fault tolerant ALU derived from our proposed single-bit module to show the proposed circuit can be extended to any larger size. The proposed circuit is implemented in the Qiskit simulation tool, and output results confirm the accuracy of our design functionality. The proposed full adder/ subtractor achieves an average of 64% and 43%, and the proposed ALU circuit achieves an average of 38% and 27% improvement in T-count and T-depth, respectively compared to their counterparts. The proposed reversible quantum-optimized fault tolerant adder/subtractor and ALU units can be applied as the basic part of DSP systems and quantum processor units in quantum computing devices.