We have designed a 16 kbit superconducting latching/SFQ hybrid (SLASH) RAM, which enables high-frequency clock operation up to 10 GHz. The 16 kbit SLASH RAM consists of four 4 × 4 matrix arrays of 256 bit RAM blocks, block decoders, latching block drivers, latching block senses, impedance matched lines and the powering circuits. The 256 bit RAM block is composed of a 16 × 16 matrix array of vortex transitional memory cells, latching drivers, SFQ NOR decoders and latching sense circuits. We have also designed and implemented an SFQ NOR decoder that is composed of magnetically coupled multi-input OR gates and RSFQ inverters.We have designed a 16 kbit superconducting latching/SFQ hybrid (SLASH) RAM, which enables high-frequency clock operation up to 10 GHz. The 16 kbit SLASH RAM consists of four 4 × 4 matrix arrays of 256 bit RAM blocks, block decoders, latching block drivers, latching block senses, impedance matched lines and the powering circuits. The 256 bit RAM block is composed of a 16 × 16 matrix array of vortex transitional memory cells, latching drivers, SFQ NOR decoders and latching sense circuits. We have also designed and implemented an SFQ NOR decoder that is composed of magnetically coupled multi-input OR gates and RSFQ inverters.

Superconductor Science and TechnologyNov 1, 199919 citations

Superconductor Logic

ScienceJun 8, 20060 citations

Superconducting latching/SFQ hybrid RAM

Shuichi Nagasawa, H. Hasegawa, T. Hashimoto +3 more

We have developed a 256-bit superconducting latching/SFQ hybrid (SLASH) RAM block as the first step in developing a 16-Kbit SLASH RAM, which enables high-frequency clock operation up to 10 GHz. The SLASH RAM is composed of ac-powered latching devices and dc-powered SFQ devices. The 256-bit SLASH RAM block is composed of 16/spl times/16 matrix array of vortex transitional memory cells, SFQ-NOR decoders, latching drivers, latching sense circuits, and address buffers. The 256-bit SLASH RAM block chips were fabricated and tested. We confirmed that the 256-bit SLASH RAM block functioned successfully.We have developed a 256-bit superconducting latching/SFQ hybrid (SLASH) RAM block as the first step in developing a 16-Kbit SLASH RAM, which enables high-frequency clock operation up to 10 GHz. The SLASH RAM is composed of ac-powered latching devices and dc-powered SFQ devices. The 256-bit SLASH RAM block is composed of 16/spl times/16 matrix array of vortex transitional memory cells, SFQ-NOR decoders, latching drivers, latching sense circuits, and address buffers. The 256-bit SLASH RAM block chips were fabricated and tested. We confirmed that the 256-bit SLASH RAM block functioned successfully.

IEEE Transactions on Applied SuperconductivityMar 1, 20018 citations

The quantum decoder

Hafiz Md. Hasan Babu

Institute of Physics eBooksJun 1, 20230 citations

The quantum decoder

Hafiz Md. Hasan Babu

Institute of Physics eBooksMay 1, 20200 citations

QECOOL: On-Line Quantum Error Correction with a Superconducting Decoder for Surface Code

Yosuke Ueno, Masaaki Kondo, Masamitsu Tanaka +2 more

Due to the low error tolerance of a qubit, detecting and correcting errors on it is essential for fault-tolerant quantum computing. Surface code (SC) associated with its decoding algorithm is one of the most promising quantum error correction (QEC) methods. QEC needs to be very power-efficient since the power budget is limited inside of a dilution refrigerator for superconducting qubits by which one of the most successful quantum computers (QCs) is built. In this paper, we propose an online-QEC algorithm and its hardware implementation with SFQ based superconducting digital circuits. We design a key building block of the proposed hardware with an SFQ cell library and evaluate it by the SPICE-level simulation. Each logic element is composed of about 3000 Josephson junctions and power consumption is about $2.78 \mu \mathrm{W}$ when operating with 2 GHz clock frequency which meets the required decoding speed. Our decoder is simulated on a quantum error simulator for code distances 5 to 13 and achieves a 1.0% accuracy threshold.Due to the low error tolerance of a qubit, detecting and correcting errors on it is essential for fault-tolerant quantum computing. Surface code (SC) associated with its decoding algorithm is one of the most promising quantum error correction (QEC) methods. QEC needs to be very power-efficient since the power budget is limited inside of a dilution refrigerator for superconducting qubits by which one of the most successful quantum computers (QCs) is built. In this paper, we propose an online-QEC algorithm and its hardware implementation with SFQ based superconducting digital circuits. We design a key building block of the proposed hardware with an SFQ cell library and evaluate it by the SPICE-level simulation. Each logic element is composed of about 3000 Josephson junctions and power consumption is about $2.78 \mu \mathrm{W}$ when operating with 2 GHz clock frequency which meets the required decoding speed. Our decoder is simulated on a quantum error simulator for code distances 5 to 13 and achieves a 1.0% accuracy threshold.

arXiv:2103.14209ACM/IEEE Design Automation Conference (DAC)Nov 8, 202153 citations

2.78 \mu \mathrm{W}

when operating with 2 GHz clock frequency which meets the required decoding speed. Our decoder is simulated on a quantum error simulator for code distances 5 to 13 and achieves a 1.0% accuracy threshold.