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網際網路技術學刊

FiT-PA: Fixed Scale FFT Based Privacy Amplification Algorithm for Quantum Key Distribution

Bo Liu, Baokang Zhao, Wanrong Yu, Chunqing Wu

Published Mar 1, 2016• 9 citations
Publisher

Abstract

Quantum Key Distribution (QKD) technology, based on basic principles of quantum mechanics, can generate unconditional security keys for communication parties. Privacy amplification, which ensures the security of generated keys, is the most significant procedure of QKD systems. Focusing on meeting the real-time and highperformance requirements of GHz high-speed QKD systems, we proposed a novel Fixed Scale FFT based Privacy Amplification (FiT-PA) algorithm and implemented on MIC platform efficiently. The experimental results show the efficiency of FiT-PA algorithm. The throughput of FiTPA algorithm reaches to 60.443 Mbps with the raw key length of 12.8 M. FiT-PA algorithm can satisfy the real-time performance demands of GHz high-speed QKD systems.

DOI
10.6138/jit.2016.17.2.20150703e

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Quantum Key Distribution (QKD) technology, based on basic principles of quantum mechanics, can generate unconditional security keys for communication parties. Privacy amplification, which ensures the security of generated keys, is the most significant procedure of QKD systems. Focusing on meeting the real-time and highperformance requirements of GHz high-speed QKD systems, we proposed a novel Fixed Scale FFT based Privacy Amplification (FiT-PA) algorithm and implemented on MIC platform efficiently. The experimental results show the efficiency of FiT-PA algorithm. The throughput of FiTPA algorithm reaches to 60.443 Mbps with the raw key length of 12.8 M. FiT-PA algorithm can satisfy the real-time performance demands of GHz high-speed QKD systems.
State-of-art quantum key distribution (QKD) systems are performed with several GHz pulse rates, meanwhile privacy amplification (PA) with large scale inputs has to be performed to generate the final secure keys with quantified security. In this paper, we propose a fast Fourier transform (FFT) enhanced high-speed and large-scale (HiLS) PA scheme on commercial CPU platform without increasing dedicated computational devices. The long input weak secure key is divided into many blocks and the random seed for constructing Toeplitz matrix is shuffled to multiple sub-sequences respectively, then PA procedures are parallel implemented for all sub-key blocks with correlated sub-sequences, afterwards, the outcomes are merged as the final secure key. When the input scale is 128 Mb, our proposed HiLS PA scheme reaches 71.16 Mbps, 54.08 Mbps and 39.15 Mbps with the compression ratio equals to 0.125, 0.25 and 0.375 respectively, resulting achievable secure key generation rates close to the asymptotic limit. HiLS PA scheme can be applied to 10 GHz QKD systems with even larger input scales and the evaluated throughput is around 32.49 Mbps with the compression ratio equals to 0.125 and the input scale of 1 Gb, which is ten times larger than the previous works for QKD systems. Furthermore, with the limited computational resources, the achieved throughput of HiLS PA scheme is 0.44 Mbps with the compression ratio equals to 0.125, when the input scale equals up to 128 Gb. In theory, the PA of the randomness extraction in quantum random number generation (QRNG) is same as the PA procedure in QKD, and our work can also be efficiently performed in high-speed QRNG.
Privacy amplification (PA) is an essential process for high-speed and real-time implementation of a continuous-variable quantum key distribution (CV-QKD) system. This work focuses on the improvement of the performance of PA, and we realize PA with Toeplitz matrix and accelerate it using fast Fourier transform (FFT) on graphic processing unit (GPU). Based on the architectural feature of FFT, we adjust its form of input length and obtained an average speed of PA about 2Gbps with input length ranges from 1Mbits to 128Mbits, which is length-adaptable to satisfy various requirements of CV-QKD systems at different transmission distances. Furthermore, we test this work with different compress ratios of PA, which can also achieve a high implementation speed around 2Gbps. With the method used in this paper, the requirements of PA for the high-speed and real-time CV-QKD system can be entirely satisfied.
Privacy amplification (PA) is a vital procedure in quantum key distribution (QKD) to shrink the eavesdropper's information about the final key almost to zero. With the increase of repeat frequency of discrete variable QKD (DV-QKD) system, PA processing speed has become the bottleneck in many high-speed DV-QKD systems. In this paper, a high-speed adaptive field-programmable gate array (FPGA)-based PA scheme using a fast Fourier transform (FFT) is presented. To decrease the computation complexity, a modified 2-D FFT-based Toeplitz PA scheme is designed. To increase the processing speed of the scheme on the constraint of limited resources, a real-value oriented FFT acceleration method and a fast read/write balanced matrix transposition method are designed and implemented in our scheme. The experimental results on a Xilinx Virtex-6 FPGA demonstrate that the throughput is nearly double of the latest FPGA based Toeplitz PA scheme according to the literature. Besides, this scheme owns not only the good adaptivity to compression ratio but also the compression ratio independent resource consumption. Therefore, this scheme can fit many high-speed QKD applications.
Abstract Privacy Amplification (PA) is indispensable in Quantum Key Distribution (QKD), ensuring security against eavesdropping by eliminating information leakage. For Discrete-Variable QKD (DV-QKD) protocols, a large input block size exceeding 108 bits is preferred to achieve the secure key rate approaching the asymptotic limit. However, in state-of-the-art quantum key distribution systems operating at multi-GHz pulse rates, PA becomes a critical bottleneck due to the conflicting requirements of large input block sizes and high throughput. To address this challenge, we propose a novel PA algorithm utilizing a newly constructed universal hash family DM3H and prove its cryptographic security rigorously. Based on the PA algorithm, we design and implement an efficient PA scheme which is capable of processing input block sizes up to 10 10 bits while achieving high throughput performance. For an input block size of 1010 bits, the implementation on the i9-14900 platform demonstrates a throughput of 112 Mbps with a retention ratio of 0.33. This breakthrough significantly enhances the secure key rate and maximum transmission distance of DV-QKD systems.
Privacy amplification (PA) is a vital procedure in quantum key distribution (QKD) to generate the secret key that the eavesdropper has only negligible information from the identical correcting key for the communicating parties. With the increase of repeat frequency of discrete-variable QKD (DV-QKD) system, the processing speed of PA has become the bottle neck restricting DV-QKD's secure key rate. The PA using Toeplitz-based Hash function is adopted widely because of its simplicity and parallel feature. Because this algorithm can be accelerated with Fast Fourier Transform (FFT), an improved scheme PA for Field-programmable Gate Array (FPGA) based on this is proposed. This paper improves the custom FFT-based algorithm by reducing the number of computations and read/write memory operations significantly. The correctness is verified when implemented in a Xilinx Virtex-6 FPGA. Meanwhile, the processing speed of improved scheme can nearly double the classical Toeplitz Hashing scheme on FPGA through the actual experiment.
The FPGA-based Quantum key distribution (QKD) system is an important trend of QKD systems. It has several advantages, real time, low power consumption and high integration density. Privacy amplification is an essential part in a QKD system to ensure the security of QKD. Existing FPGA-based privacy amplification schemes have an disadvantage, that the throughput and the input size of these schemes (the best scheme 116Mbps@10^6) are much lower than these on other platforms (the best scheme 1Gbps@10^8). This paper designs a new PA scheme for FPGA-based QKD with multilinear modular hash-modular arithmetic hash (MMH-MH) PA and number theoretical transform (NTT) algorithm. The new PA scheme, named large-scale and high-speed (LSHS) PA scheme, designs a multiplication-reusable architecture and three key units to improve the performance. This scheme improves the input size and throughput of PA by above an order of magnitude. The throughput and input size of this scheme (1Gbps@10^8) is at a comparable level with these on other platforms.