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arXiv:2503.09331

Large-Scale FPGA-Based Privacy Amplification Exceeding $10^8$ Bits for Quantum Key Distribution

Xi Cheng, Haokun Mao, Hongwei Xu, Qiong Li

Published Mar 12, 2025• 1 citation
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Abstract

Privacy Amplification (PA) is indispensable in Quantum Key Distribution (QKD) post-processing, as it eliminates information leakage to eavesdroppers. Field-programmable gate arrays (FPGAs) are highly attractive for QKD systems due to their flexibility and high integration. However, due to limited resources, input and output sizes remain the primary bottleneck in FPGA-based PA schemes for Discrete Variable (DV)-QKD systems. In this paper, we present a large-scale FPGA-based PA scheme that supports both input block sizes and output key sizes exceeding $10^8$ bits, effectively addressing the challenges posed by the finite-size effect. To accommodate the large input and output sizes, we propose a novel PA algorithm and prove its security. We implement and evaluate this scheme on a Xilinx XCKU095 FPGA platform. Experimental results demonstrate that our PA implementation can handle an input block size of $10^8$ bits with flexible output sizes up to the input size. For DV-QKD systems, our PA scheme supports an input block size nearly two orders of magnitude larger than current FPGA-based PA schemes, significantly mitigating the impact of the finite-size effect on the final secure key rate.

DOI
10.48550/arxiv.2503.09331

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Large-Scale FPGA-Based Privacy Amplification Exceeding 10810^8108 Bits for Quantum Key Distribution
Privacy Amplification (PA) is indispensable in Quantum Key Distribution (QKD) post-processing, as it eliminates information leakage to eavesdroppers. Field-programmable gate arrays (FPGAs) are highly attractive for QKD systems due to their flexibility and high integration. However, due to limited resources, input and output sizes remain the primary bottleneck in FPGA-based PA schemes for Discrete Variable (DV)-QKD systems. In this paper, we present a large-scale FPGA-based PA scheme that supports both input block sizes and output key sizes exceeding 10810^8108 bits, effectively addressing the challenges posed by the finite-size effect. To accommodate the large input and output sizes, we propose a novel PA algorithm and prove its security. We implement and evaluate this scheme on a Xilinx XCKU095 FPGA platform. Experimental results demonstrate that our PA implementation can handle an input block size of 10810^8108 bits with flexible output sizes up to the input size. For DV-QKD systems, our PA scheme supports an input block size nearly two orders of magnitude larger than current FPGA-based PA schemes, significantly mitigating the impact of the finite-size effect on the final secure key rate.
Abstract Privacy Amplification (PA) is indispensable in Quantum Key Distribution (QKD), ensuring security against eavesdropping by eliminating information leakage. For Discrete-Variable QKD (DV-QKD) protocols, a large input block size exceeding 108 bits is preferred to achieve the secure key rate approaching the asymptotic limit. However, in state-of-the-art quantum key distribution systems operating at multi-GHz pulse rates, PA becomes a critical bottleneck due to the conflicting requirements of large input block sizes and high throughput. To address this challenge, we propose a novel PA algorithm utilizing a newly constructed universal hash family DM3H and prove its cryptographic security rigorously. Based on the PA algorithm, we design and implement an efficient PA scheme which is capable of processing input block sizes up to 10 10 bits while achieving high throughput performance. For an input block size of 1010 bits, the implementation on the i9-14900 platform demonstrates a throughput of 112 Mbps with a retention ratio of 0.33. This breakthrough significantly enhances the secure key rate and maximum transmission distance of DV-QKD systems.
In a quantum key distribution (QKD) system, privacy amplification (PA) is an essential procedure that can effectively eliminate the leaked information to an eavesdropper and distill a secret key. The processing speed of the PA algorithm inevitably affects the final key rate of the QKD system. We propose a high-speed PA algorithm based on field-programmable gate array (FPGA), where the matrix multiplications are divided into a number of rhomboid-block operations. The implementation of the PA reduces significantly the required number of FPGA Block RAMs. Meanwhile, it automatically adapts to different lengths of input and output blocks. Finally, we verified the correctness and high-speed of the algorithm when implemented in a Xilinx Virtex-7 FPGA.
Privacy amplification (PA) is a critical process in quantum key distribution (QKD) systems, essential for eliminating information leakage to eavesdroppers and extracting unconditionally secure keys. In practical high-speed QKD systems, a large input size enables the PA scheme to approach the asymptotic limit of the secure-key rate. Concurrently, the throughput of the PA scheme must keep pace with the GHz-level clock rates of modern QKD systems to prevent it from becoming a systemic bottleneck. To globally optimize these objectives, this paper proposes a scalable and highly efficient PA scheme combining a novel δ-almost-universal hash family (FM3H) with modular arithmetic hashing (MH), and proves the security of this hybrid scheme, within the information-theoretic and quantum-side framework. The proposed scheme achieves a throughput of 283 Mbps on a common mobile CPU with an input size of 1010 bits. NIST statistical tests and avalanche-effect measurements are reported as characterizations of the statistical properties of the output sequences. To our knowledge, this work presents the first FPGA-based implementation of a modular hashing-based PA scheme, thereby breaking the dependence of modular hashing schemes on general software platforms. In DV-QKD systems, the FPGA-based scheme achieves a throughput of 1.706 Gbps while maintaining low resource overhead.
In this paper, a high-performance field-programmable gate array (FPGA) based privacy amplification (PA) scheme for both continuous variable and discrete variable - quantum key distribution (QKD) is presented, which can provide more than 1.5 Gbps throughput at the input block size close to10810^{8}108. Besides, the resource consumption is so economical that there is no need of any external storage. To the best of our knowledge, our scheme outperforms existing FPGA based PA schemes by over an order of magnitude in terms of throughput and input block size. To achieve this feature, we design a novel FPGA-based hybrid hash PA algorithm combining multilinear modular hash and modular arithmetic hash (MMH-MH) based on number theoretical transform (NTT). Based on the hybrid hash algorithm, many optimization strategies are designed in our FPGA based PA scheme, such as an NTT-based optimization unit, an NTT-reusable architecture, a memory-saving modular accumulation unit for multilinear modular hash and a pipelined binary modulo unit for modular arithmetic hash. Plentiful experiment results demonstrate the high performance and reliability of our scheme. It can be embedded in most standalone QKD devices conveniently. What's more, it is also a good candidate for a chip-based QKD system.
Privacy amplification (PA) is a vital procedure in quantum key distribution (QKD) to shrink the eavesdropper's information about the final key almost to zero. With the increase of repeat frequency of discrete variable QKD (DV-QKD) system, PA processing speed has become the bottleneck in many high-speed DV-QKD systems. In this paper, a high-speed adaptive field-programmable gate array (FPGA)-based PA scheme using a fast Fourier transform (FFT) is presented. To decrease the computation complexity, a modified 2-D FFT-based Toeplitz PA scheme is designed. To increase the processing speed of the scheme on the constraint of limited resources, a real-value oriented FFT acceleration method and a fast read/write balanced matrix transposition method are designed and implemented in our scheme. The experimental results on a Xilinx Virtex-6 FPGA demonstrate that the throughput is nearly double of the latest FPGA based Toeplitz PA scheme according to the literature. Besides, this scheme owns not only the good adaptivity to compression ratio but also the compression ratio independent resource consumption. Therefore, this scheme can fit many high-speed QKD applications.
Privacy amplification (PA) is a vital procedure in quantum key distribution (QKD) to generate the secret key that the eavesdropper has only negligible information from the identical correcting key for the communicating parties. With the increase of repeat frequency of discrete-variable QKD (DV-QKD) system, the processing speed of PA has become the bottle neck restricting DV-QKD's secure key rate. The PA using Toeplitz-based Hash function is adopted widely because of its simplicity and parallel feature. Because this algorithm can be accelerated with Fast Fourier Transform (FFT), an improved scheme PA for Field-programmable Gate Array (FPGA) based on this is proposed. This paper improves the custom FFT-based algorithm by reducing the number of computations and read/write memory operations significantly. The correctness is verified when implemented in a Xilinx Virtex-6 FPGA. Meanwhile, the processing speed of improved scheme can nearly double the classical Toeplitz Hashing scheme on FPGA through the actual experiment.