Privacy amplification (PA) is a vital procedure in quantum key distribution (QKD) to generate the secret key that the eavesdropper has only negligible information from the identical correcting key for the communicating parties. With the increase of repeat frequency of discrete-variable QKD (DV-QKD) system, the processing speed of PA has become the bottle neck restricting DV-QKD's secure key rate. The PA using Toeplitz-based Hash function is adopted widely because of its simplicity and parallel feature. Because this algorithm can be accelerated with Fast Fourier Transform (FFT), an improved scheme PA for Field-programmable Gate Array (FPGA) based on this is proposed. This paper improves the custom FFT-based algorithm by reducing the number of computations and read/write memory operations significantly. The correctness is verified when implemented in a Xilinx Virtex-6 FPGA. Meanwhile, the processing speed of improved scheme can nearly double the classical Toeplitz Hashing scheme on FPGA through the actual experiment.
Privacy amplification (PA) is a vital procedure in quantum key distribution (QKD) to generate the secret key that the eavesdropper has only negligible information from the identical correcting key for the communicating parties. With the increase of repeat frequency of discrete-variable QKD (DV-QKD) system, the processing speed of PA has become the bottle neck restricting DV-QKD's secure key rate. The PA using Toeplitz-based Hash function is adopted widely because of its simplicity and parallel feature. Because this algorithm can be accelerated with Fast Fourier Transform (FFT), an improved scheme PA for Field-programmable Gate Array (FPGA) based on this is proposed. This paper improves the custom FFT-based algorithm by reducing the number of computations and read/write memory operations significantly. The correctness is verified when implemented in a Xilinx Virtex-6 FPGA. Meanwhile, the processing speed of improved scheme can nearly double the classical Toeplitz Hashing scheme on FPGA through the actual experiment.
Privacy amplification (PA) is a vital procedure in quantum key distribution (QKD) to shrink the eavesdropper's information about the final key almost to zero. With the increase of repeat frequency of discrete variable QKD (DV-QKD) system, PA processing speed has become the bottleneck in many high-speed DV-QKD systems. In this paper, a high-speed adaptive field-programmable gate array (FPGA)-based PA scheme using a fast Fourier transform (FFT) is presented. To decrease the computation complexity, a modified 2-D FFT-based Toeplitz PA scheme is designed. To increase the processing speed of the scheme on the constraint of limited resources, a real-value oriented FFT acceleration method and a fast read/write balanced matrix transposition method are designed and implemented in our scheme. The experimental results on a Xilinx Virtex-6 FPGA demonstrate that the throughput is nearly double of the latest FPGA based Toeplitz PA scheme according to the literature. Besides, this scheme owns not only the good adaptivity to compression ratio but also the compression ratio independent resource consumption. Therefore, this scheme can fit many high-speed QKD applications.
In a quantum key distribution (QKD) system, privacy amplification (PA) is an essential procedure that can effectively eliminate the leaked information to an eavesdropper and distill a secret key. The processing speed of the PA algorithm inevitably affects the final key rate of the QKD system. We propose a high-speed PA algorithm based on field-programmable gate array (FPGA), where the matrix multiplications are divided into a number of rhomboid-block operations. The implementation of the PA reduces significantly the required number of FPGA Block RAMs. Meanwhile, it automatically adapts to different lengths of input and output blocks. Finally, we verified the correctness and high-speed of the algorithm when implemented in a Xilinx Virtex-7 FPGA.
For a high-speed and secure continuous-variable quantum key distribution (CV-QKD) system, privacy amplification (PA) plays an important role. To reduce the finite size effect, the input length of PA should be at least on the order of 10^8, 10^9, 10^10 when the transmission distance is about 50km, 80km, 100km, respectively. This leads to high computation complexity and large storage demand of the data, which is unfriendly to field programmable gate array (FPGA) implementation for its limited resource. In addition, the limited IO speed of Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) restricts the implementation performance of PA. In this paper, we propose an effective way to access data based on DDR to improve the performance of PA. As a result, the reading time from DDR can be reduced, and it can eliminate the effect of the limited IO speed of DDR, so that PA can perform with multiple code-words. This can make full use of the resource of FPGA and increase the execution speed of PA. Besides, combining with the proposed method, an easier algorithm is used to decrease the complexity of calculations. Based on these methods, we realize PA with Toeplitz matrix based on FPGA and the experimental throughput is about 288Mbps when the input length is about 100Mbits.
Privacy amplification (PA) is an essential process for high-speed and real-time implementation of a continuous-variable quantum key distribution (CV-QKD) system. This work focuses on the improvement of the performance of PA, and we realize PA with Toeplitz matrix and accelerate it using fast Fourier transform (FFT) on graphic processing unit (GPU). Based on the architectural feature of FFT, we adjust its form of input length and obtained an average speed of PA about 2Gbps with input length ranges from 1Mbits to 128Mbits, which is length-adaptable to satisfy various requirements of CV-QKD systems at different transmission distances. Furthermore, we test this work with different compress ratios of PA, which can also achieve a high implementation speed around 2Gbps. With the method used in this paper, the requirements of PA for the high-speed and real-time CV-QKD system can be entirely satisfied.
ABSTRACT Privacy amplification (PA) is a crucial step in Quantum Key Distribution (QKD). The original key with the risk of information leakage is transformed into the final key with information theory security through PA. The speed of PA limits the overall rate of QKD. This article proposes a novel approach of PA. This method connects Square Hash (SQH) and number‐theory transform Hash (NH) in series and utilizes number‐theoretic fast Fourier transform (NTT) to reduce its computational complexity to . This paper provides a security proof based on information theory. To implement the scheme based on field programmable gate arrays (FPGA), this paper designed a new architecture to support it. Several optimization techniques of the PA scheme have been implemented to accelerate computation speed and reduce resource consumption, including parallel NTT computation unit and pipelined carry unit, etc. This architecture is also applicable to other similar PA scheme. The experiment result achieves a higher throughput than the compared FPGA‐based works. After further optimization of the architecture, the clock frequency reaches 250 MHz, and the throughput exceeds 10 Gbps, achieving more than 6 times higher than the fastest PA solution among the compared works.
Large-Scale FPGA-Based Privacy Amplification Exceeding 108 Bits for Quantum Key Distribution
Privacy Amplification (PA) is indispensable in Quantum Key Distribution (QKD) post-processing, as it eliminates information leakage to eavesdroppers. Field-programmable gate arrays (FPGAs) are highly attractive for QKD systems due to their flexibility and high integration. However, due to limited resources, input and output sizes remain the primary bottleneck in FPGA-based PA schemes for Discrete Variable (DV)-QKD systems. In this paper, we present a large-scale FPGA-based PA scheme that supports both input block sizes and output key sizes exceeding 108 bits, effectively addressing the challenges posed by the finite-size effect. To accommodate the large input and output sizes, we propose a novel PA algorithm and prove its security. We implement and evaluate this scheme on a Xilinx XCKU095 FPGA platform. Experimental results demonstrate that our PA implementation can handle an input block size of 108 bits with flexible output sizes up to the input size. For DV-QKD systems, our PA scheme supports an input block size nearly two orders of magnitude larger than current FPGA-based PA schemes, significantly mitigating the impact of the finite-size effect on the final secure key rate.