All Refractory Josephson Integration Process with NbN Junctions

S. Takada

Masahiro Aoyagi, Alexandre Shoji, S. Kosaka +2 more

Submicron NbN/MgO/NbN Josephson tunnel junctions for Josephson integrated circuits were investigated. The junctions have been fabricated by the cross-line patterning (CLIP) method with an electron-beam (EB) direct-writing technique. The all-refractory fabrication process for logic circuits using the CLIP method is presented. This process is applied to the fabrication of a logic gate of 4JL containing 0.8- mu m-square junctions as an example of digital application. A logic gate has been fabricated by this process, and its characteristics are discussed.>

Alexandre Shoji

S. Kosaka, Fujitoshi Shinoki, S. Takada +1 more

We have developed a new integration method for Josephson tunnel junctions based on high Tc superconducting compound materials such as NbN. In this method, a sputtered ZnO film has been employed as a resist mask which can be used in high substrate temperatures during the film deposition. It has been found that fine patterns of the refractory superconducting film can be obtained by this method and the patterning processes have no interference with other integration processes. We have applied this method to patterning base electrode of NbN and formed high quality NbN-oxide-Pb Josephson tunnel junctions by using an rf plasma oxidation. The fabricated junctions have been found to have a relatively large gap ( ∼ 4.0 mV ) and low current leak in the subgap region, and to be quite stable for thermal cyclings and storage. We have also fabricated quantum interference memory devices by integrating these junctions and the operation has been successfully demonstrated.

D. W. Jillie, L. N. Smith, Harry Kroger

Alexandre Shoji, S. Kosaka, Fujitoshi Shinoki +2 more

We have developed a novel process for fabricating all refractory Josephson tunnel junctions whose base and counter electrodes are composed of (Nb-NbN) double-layered films. In this process, tunnel junctions have been isolated using a reactive ion etching from a junction sandwich which had been formed on an entire silicon wafer, and also the reactive ion etching has been used for patterning electrodes and insulation layers in devices. Fabricated junctions have yielded good tunneling characteristics with excellent uniformity and reproducibility. The maximum critical current density was widely changed from 300 A/cm2to 8 kA/cm2. All refractory single flux quantum(SFQ) memory cells in a 32×32 arrangement have been integrated with a 2.5 μm minimum linewidth on a chip using this process, and an SFQ cell in the memory array has been successfully operated. The maximum deviation of critical currents in the memory array was measured to be ±6.5%.