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Journal of Tsinghua University(Science and Technology)

Efficient quantization algorithm for low-density parity-check code decoding

Jianhua Lü

Published Jan 1, 2007• 0 citations
OpenAlex

Abstract

A variable step uniform quantization(VSUQ) sum-product algorithm(SPA) was developed to reduce the hardware complexity of low-density parity-check(LDPC) code decoding.The extrinsic information in the check nodes and bit nodes is quantized in the same quantization step.Then,the quantization steps for the check nodes and bit nodes are multiplied and divided by a predetermined parameter.Simulation and implementation using a field programmable gate array(FPGA) show that the performance degradation in the algorithm is within 0.1 dB comparing to the unquantized standard SPA,while reducing the hardware size by 50% comparing to a uniform quantization SPA with the same performance.

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A variable step uniform quantization(VSUQ) sum-product algorithm(SPA) was developed to reduce the hardware complexity of low-density parity-check(LDPC) code decoding.The extrinsic information in the check nodes and bit nodes is quantized in the same quantization step.Then,the quantization steps for the check nodes and bit nodes are multiplied and divided by a predetermined parameter.Simulation and implementation using a field programmable gate array(FPGA) show that the performance degradation in the algorithm is within 0.1 dB comparing to the unquantized standard SPA,while reducing the hardware size by 50% comparing to a uniform quantization SPA with the same performance.
In this paper, we propose low complexity implementations of sum-product algorithm (SPA) for decoding low-density parity-check (LDPC) codes. The finite precision implementations for SPA have an important tradeoff between the decoding performance and hardware complexity caused by two dominant area consuming factors. One is the memory for updated messages storage and the other is the look-up table (LUT) for implementation of nonlinear function Psi(x). The proposed two types of variable quantization schemes result in significant reductions of LUT sizes. Computer simulation results indicate that the performance losses of SPA with reduced LUT by proposed schemes are less than 0.05 dB compared to that of SPA with original LUT. Moreover, the proposed implementation offers a large reduction in the finite wordlength for storage of updated messages using a kind of compression technique without performance losses. As a result, using the proposed implementation based on variable quantization scheme and data compression technique, the novel proposed implementation for SPA decoder architecture offers significant reductions of 75% and 33% in hardware complexities of LUT and memories, respectively, without significant performance degradations over conventional uniform quantization scheme. Furthermore, since each LUT with variable (6:3) quantization scheme II has only 8 entries, its hardware implementation can be replaced with a small combination circuit instead of readonly-memory (ROM) for LUT
In this paper, a non-uniform quantization scheme is proposed for the decoding of Low-Density Parity-Check (LDPC) codes with the Sum-Product Algorithm (SPA). With the proposed scheme, the quantization-range and quantization-interval for the soft Log-Likelihood-Ratio (LLR) values of the decoder input, the variable nodes, and the check nodes are set separately, and are also adjusted according to the evolution of the probability density distribution of the LLR values in the iterative decoding procedure to minimize the difference between the decoding values before quantization and that after quantization. Simulation results show that decoding with 3-bit non-uniform quantization of the proposed scheme may obtain a BER performance slightly better than that of decoding with 6-bits quantization of the traditional uniform quantization method.
of the Dissertation Quantization of a Low-Density Parity-Check (LDPC) Decoder: Limited-Precision Digital Design of the Sum-Product Algorithm (SPA) for Wireless Voice and Video Communication Channels. by Raymond B Moberly Claremont Graduate University and San Diego State University: 2012 This dissertation presents two-bit and three-bit quantizations for Sum Product Algorithm (SPA) decoding of Low-Density Parity-Check (LDPC) codes. The study involves evaluation of both decoding performance and hardware implementation requirements. Trade-o s between these factors are considered. The quantizations are simulated in software to measure decoding performance. While quantization e ects are the focal point of the research, a comparison of the number of decoding iterations and of the number of bits of precision used in the decoder are both presented along with the quantization experiments. Decoder performance, measured in terms of both Bit Error Rate (BER) and Frame Error Rate (FER), is tested for each two-bit and three-bit quantization over a range of Signal to Noise Ratio (SNR) values. No single quantization outperforms all other quantizations for the entire tested SNR range. Analysis of the SPA is performed, revealing strategies for computational e ciency and digital design. The hardware designs combine the parity-check and variable-node update steps of the SPA into a single update computation. The update computation is implemented in a hardware design language (HDL), synthesized to programmable logic, and then tested on a Field Programmable Gate Array (FPGA). Hardware implementation requirements, as measured from the synthesis results, are evaluated and compared to a selection of other published works, particularly the work of Planjery et al. A exible implementation is proposed that can adapt the quantization as the channel conditions change.
An efficient implementation of the Sum-Product algorithm(SPA) in the log-likelihood ratio (LLR) domain is presented in [1]. In this paper, We modify a formula in [1] such that SPA can be implemented by using two small look-up tables. With this modification, all the calculations involved in this implementation involve only additions, subtractions, comparisons and table looking-ups, which leads to low computation complexity and facility in hardware implementation. Based on this modified implementation, various quantization schemes of SPA for decoding low-density parity-check (LDPC) codes are investigated. And the issues related to quantization, such as clipping levels and variables quantization, are also investigated. Simulation results show that the performance of the uniform quantization scheme is very close to that of the non-quantizaiton over the AWGN channel. Moreover, it can obtain the same performance as that of non-quantization at high SNRs.
In this paper, an improved low-complexity sum-product decoding algorithm is presented for low-density parity-check (LDPC) codes. In the proposed algorithm, reduction in computational complexity is achieved by utilizing fast Fourier transform (FFT) with time shift in the check node process. The improvement in the decoding performance is achieved by utilizing an optimized integer constant in the variable node process. Simulation results show that the proposed algorithm achieves an overall coding gain improvement ranging from 0.04 to 0.46 dB. Moreover, when compared with the sum-product algorithm (SPA), the proposed decoding algorithm can achieve a reduction of 42%–67% of the total number of arithmetic operations required for the decoding process.
Very high data rates and decoding computational complexity place strict constraints in 5G and 6G communications. In this paper, non-uniform Quantized Decoding algorithm is proposed for Low-density Parity Check codes (LDPC). In the proposed algorithm, the check node updating process is carried out using quantization, which reduces complexity. The Sum Product Algorithm (SPA) is iterative message passing decoding techniques offer the optimal performance for LDPC codes. Implementations use message-passing decoding with more precision, results extremely high complexity. In Iterative, message-passing (MP), trapping sets and absorbing sets causes low error floor. In this article non-uniform quantization proposed to overcome dynamic range of values over uniform quantization. Simulation results provide coding gain increases closer to of 0.5 dB in higher SNR and has good error floor at 10−5.