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SiPS ... design and implementation - IEEE Workshop on Signal Processing Systems

Low Complexity Implementations of Sum-Product Algorithm for Decoding Low-Density Parity-Check Codes

Daesun Oh, Keshab K. Parhi

Published Oct 1, 2006• 18 citations

Abstract

In this paper, we propose low complexity implementations of sum-product algorithm (SPA) for decoding low-density parity-check (LDPC) codes. The finite precision implementations for SPA have an important tradeoff between the decoding performance and hardware complexity caused by two dominant area consuming factors. One is the memory for updated messages storage and the other is the look-up table (LUT) for implementation of nonlinear function Psi(x). The proposed two types of variable quantization schemes result in significant reductions of LUT sizes. Computer simulation results indicate that the performance losses of SPA with reduced LUT by proposed schemes are less than 0.05 dB compared to that of SPA with original LUT. Moreover, the proposed implementation offers a large reduction in the finite wordlength for storage of updated messages using a kind of compression technique without performance losses. As a result, using the proposed implementation based on variable quantization scheme and data compression technique, the novel proposed implementation for SPA decoder architecture offers significant reductions of 75% and 33% in hardware complexities of LUT and memories, respectively, without significant performance degradations over conventional uniform quantization scheme. Furthermore, since each LUT with variable (6:3) quantization scheme II has only 8 entries, its hardware implementation can be replaced with a small combination circuit instead of readonly-memory (ROM) for LUT

DOI: 10.1109/sips.2006.352592

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In this paper, we propose low complexity implementations of sum-product algorithm (SPA) for decoding low-density parity-check (LDPC) codes. The finite precision implementations for SPA have an important tradeoff between the decoding performance and hardware complexity caused by two dominant area consuming factors. One is the memory for updated messages storage and the other is the look-up table (LUT) for implementation of nonlinear function Psi(x). The proposed two types of variable quantization schemes result in significant reductions of LUT sizes. Computer simulation results indicate that the performance losses of SPA with reduced LUT by proposed schemes are less than 0.05 dB compared to that of SPA with original LUT. Moreover, the proposed implementation offers a large reduction in the finite wordlength for storage of updated messages using a kind of compression technique without performance losses. As a result, using the proposed implementation based on variable quantization scheme and data compression technique, the novel proposed implementation for SPA decoder architecture offers significant reductions of 75% and 33% in hardware complexities of LUT and memories, respectively, without significant performance degradations over conventional uniform quantization scheme. Furthermore, since each LUT with variable (6:3) quantization scheme II has only 8 entries, its hardware implementation can be replaced with a small combination circuit instead of readonly-memory (ROM) for LUT

An efficient implementation of the Sum-Product algorithm(SPA) in the log-likelihood ratio (LLR) domain is presented in [1]. In this paper, We modify a formula in [1] such that SPA can be implemented by using two small look-up tables. With this modification, all the calculations involved in this implementation involve only additions, subtractions, comparisons and table looking-ups, which leads to low computation complexity and facility in hardware implementation. Based on this modified implementation, various quantization schemes of SPA for decoding low-density parity-check (LDPC) codes are investigated. And the issues related to quantization, such as clipping levels and variables quantization, are also investigated. Simulation results show that the performance of the uniform quantization scheme is very close to that of the non-quantizaiton over the AWGN channel. Moreover, it can obtain the same performance as that of non-quantization at high SNRs.

Efficient implementations of the sum-product algorithm (SPA) are presented for decoding low-density parity-check (LDPC) codes using log-likelihood ratios (LLR) as messages between symbol and parity-check nodes. Various reduced-complexity derivatives of the LLR-SPA are proposed. Both serial and parallel implementations are investigated, leading to trellis and tree topologies, respectively. Furthermore, by exploiting the inherent robustness of LLRs, it is shown, via simulations, that coarse quantization tables are sufficient to implement complex core operations with negligible or no loss in performance. The unified treatment of decoding techniques for LDPC codes presented here provides flexibility in selecting the appropriate design point in high-speed applications from a performance, latency and computational complexity perspective.

In this paper, we propose a low-complexity, high-efficiency two-dimensional look-up table (2D LUT) for carrying out the sum-product algorithm in the decoding of low-density parity-check (LDPC) codes. Instead of employing adders for the core operation when updating check node messages, in the proposed scheme, the main term and correction factor of the core operation are successfully merged into a compact 2D LUT. Simulation results indicate that the proposed 2D LUT not only attains close-to-optimal bit error rate performance but also enjoys a low complexity advantage that is suitable for hardware implementation.

A variable step uniform quantization(VSUQ) sum-product algorithm(SPA) was developed to reduce the hardware complexity of low-density parity-check(LDPC) code decoding.The extrinsic information in the check nodes and bit nodes is quantized in the same quantization step.Then,the quantization steps for the check nodes and bit nodes are multiplied and divided by a predetermined parameter.Simulation and implementation using a field programmable gate array(FPGA) show that the performance degradation in the algorithm is within 0.1 dB comparing to the unquantized standard SPA,while reducing the hardware size by 50% comparing to a uniform quantization SPA with the same performance.

This paper describes an efficient implementation of the Sum-Product Algorithm (SPA) within a Low Density Parity Check (LDPC) code decoder, where a horizontal process correction term is used to improve the decoding performance of the Min-Sum algorithms. The correction term is implemented as a look-up table. The algorithm uses the correction term redundancy by means of a coordinate transformation to reduce the hardware complexity. Simulations and hardware tests indicate that the decoding performance is very good with the appropriate look-up table.

of the Dissertation Quantization of a Low-Density Parity-Check (LDPC) Decoder: Limited-Precision Digital Design of the Sum-Product Algorithm (SPA) for Wireless Voice and Video Communication Channels. by Raymond B Moberly Claremont Graduate University and San Diego State University: 2012 This dissertation presents two-bit and three-bit quantizations for Sum Product Algorithm (SPA) decoding of Low-Density Parity-Check (LDPC) codes. The study involves evaluation of both decoding performance and hardware implementation requirements. Trade-o s between these factors are considered. The quantizations are simulated in software to measure decoding performance. While quantization e ects are the focal point of the research, a comparison of the number of decoding iterations and of the number of bits of precision used in the decoder are both presented along with the quantization experiments. Decoder performance, measured in terms of both Bit Error Rate (BER) and Frame Error Rate (FER), is tested for each two-bit and three-bit quantization over a range of Signal to Noise Ratio (SNR) values. No single quantization outperforms all other quantizations for the entire tested SNR range. Analysis of the SPA is performed, revealing strategies for computational e ciency and digital design. The hardware designs combine the parity-check and variable-node update steps of the SPA into a single update computation. The update computation is implemented in a hardware design language (HDL), synthesized to programmable logic, and then tested on a Field Programmable Gate Array (FPGA). Hardware implementation requirements, as measured from the synthesis results, are evaluated and compared to a selection of other published works, particularly the work of Planjery et al. A exible implementation is proposed that can adapt the quantization as the channel conditions change.