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IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences

A Low-Complexity and High-Performance 2D Look-Up Table for LDPC Hardware Implementation

Jung-Chieh Chen, Po-Hui Yang, Jenn‐Kaie Lain, Tzu-Wen CHUNG

Published Jan 1, 2009• 0 citations
Publisher

Abstract

In this paper, we propose a low-complexity, high-efficiency two-dimensional look-up table (2D LUT) for carrying out the sum-product algorithm in the decoding of low-density parity-check (LDPC) codes. Instead of employing adders for the core operation when updating check node messages, in the proposed scheme, the main term and correction factor of the core operation are successfully merged into a compact 2D LUT. Simulation results indicate that the proposed 2D LUT not only attains close-to-optimal bit error rate performance but also enjoys a low complexity advantage that is suitable for hardware implementation.

DOI
10.1587/transfun.e92.a.2941

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In this paper, we propose low complexity implementations of sum-product algorithm (SPA) for decoding low-density parity-check (LDPC) codes. The finite precision implementations for SPA have an important tradeoff between the decoding performance and hardware complexity caused by two dominant area consuming factors. One is the memory for updated messages storage and the other is the look-up table (LUT) for implementation of nonlinear function Psi(x). The proposed two types of variable quantization schemes result in significant reductions of LUT sizes. Computer simulation results indicate that the performance losses of SPA with reduced LUT by proposed schemes are less than 0.05 dB compared to that of SPA with original LUT. Moreover, the proposed implementation offers a large reduction in the finite wordlength for storage of updated messages using a kind of compression technique without performance losses. As a result, using the proposed implementation based on variable quantization scheme and data compression technique, the novel proposed implementation for SPA decoder architecture offers significant reductions of 75% and 33% in hardware complexities of LUT and memories, respectively, without significant performance degradations over conventional uniform quantization scheme. Furthermore, since each LUT with variable (6:3) quantization scheme II has only 8 entries, its hardware implementation can be replaced with a small combination circuit instead of readonly-memory (ROM) for LUT
An efficient implementation of the Sum-Product algorithm(SPA) in the log-likelihood ratio (LLR) domain is presented in [1]. In this paper, We modify a formula in [1] such that SPA can be implemented by using two small look-up tables. With this modification, all the calculations involved in this implementation involve only additions, subtractions, comparisons and table looking-ups, which leads to low computation complexity and facility in hardware implementation. Based on this modified implementation, various quantization schemes of SPA for decoding low-density parity-check (LDPC) codes are investigated. And the issues related to quantization, such as clipping levels and variables quantization, are also investigated. Simulation results show that the performance of the uniform quantization scheme is very close to that of the non-quantizaiton over the AWGN channel. Moreover, it can obtain the same performance as that of non-quantization at high SNRs.
This paper present a novel decoding scheme for low density parity check codes (LDPC) over GF(q). The scheme is a variation of the sum-product algorithm. The novel algorithm has a low complexity and reduces the number of look up table accesses necessary. Moreover, the algorithm does not compute division or multiplication, making it suitable for hardware implementation. The new algorithm has been compared with existing algorithms showing that both the BER performance and the speed of convergence are identical.
The Belief-propagation (BP) algorithm is a powerful decoder for LDPC codes. However, the BP algorithm requires the high complexity of the check node operation. Therefore, in the previous works, a lookup table (LUT)-based decoder has been proposed for LDPC codes. In this work, we propose the LUT design for protograph LDPC codes. Our LUT design can support the parallel edge, variable node with degree-1 and punctured variable node. As a result, the coding losses of 2-, 3- and 4-bit quantization of LUT decoder are 1.6, 0.5 and 0.1 dB compared to BP algorithm.