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Journal of Information Engineering University

Serial Concatenate LDPC Codes

Shuiqing Li

Published Jan 1, 2004• 0 citations
OpenAlex

Abstract

This paper mainly discusses the design of a family of irregular LDPC codes with low encoding complexity. This class of LDPC codes concatenates multiple single bit parity check block codes in serial, and it makes encoding complexity much lower than in usual ways. Furthermore, using a AWGN channel, it demonstrates that this class of LDPC codes have very good decoding performance.

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This paper mainly discusses the design of a family of irregular LDPC codes with low encoding complexity. This class of LDPC codes concatenates multiple single bit parity check block codes in serial, and it makes encoding complexity much lower than in usual ways. Furthermore, using a AWGN channel, it demonstrates that this class of LDPC codes have very good decoding performance.
LDPC code shows a good performance with long-block codes. However, certain channels are constrained to use short-block codes due to latency. Therefore, concatenated LDPC codes with iterative decoding is a good choice to get a good performance. Concatenated binary LDPC codes were introduced as a class of concatenated codes in which the LDPC codes are irregular codes having different parameters. Although irregular LDPC codes are more efficient than regular codes, irregular LDPC codes have an error floor and a higher encoding complexity than regular code. In this paper, in order to get a good performance/complexity trade-off with a short-block code, we investigate a parallel concatenation of two identical regular binary LDPC codes, using an interleaver. Simulation results show that the proposed code outperforms a single LDPC code. The proposed code needs less time decoding delay than a single LDPC code with the same iteration number. Also, the proposed code needs a less number of iterations to achieve the same performance of a single LDPC code that leads to less decoding complexity and decoding delay. A simplified algorithm, the min-sum algorithm, that is used to decode the component codes shows a small performance loss with respect to the sum-product algorithm.
Concatenated codes are effectively used in different approaches of error-correcting theory. We suggest new concatenated code construction that is composed of outer LDPC code and a particular designed inner LDPC code. Special optimization procedure was developed to obtain inner code with specific error-correcting characteristics. We apply the decoder of woven codes to this construction, while reducing the complexity of decoding procedure compared to a classic decoder of LDPC code. Furthermore, we improve the performance of our scheme with puncturing the code symbols. The resulting concatenated construction outperforms low-rate LDPC from the 5G standard. Besides this, we demonstrate the performance of code with a special parity-check matrix consisting of parity-check matrices of inner and outer codes from our suggested construction.
In this paper, low density parity check (LDPC) codes are considered. Design techniques are examined and new LDPC codes with improved error performance are proposed for irregular LDPC codes. Especially for BPSK modulation and AWGN channel, superior LDPC codes are successfully designed for R = 0.5 and N = 1000. For the designed superior irregular codes, it can be said that not only the performance of the codes is good when the code block length goes to infinity, but also they approach to the channel capacity and for code rate R = 0.5, they perform better than their counterparts given in the literature, when the code block length is finite (N = 1000). For irregular codes, when the degree of the bit node that possess the maximum number of branches is large, then that code approaches to the channel capacity. During the optimization of the encoder and decoder blocks, a combination of differential evolution technique, bit filling and message passing algorithms are considered to reach superior codes. The best superior code proposed in the paper is an irregular LDPC code with rate R = 0.5 which is only 0.02 dB away from the channel capacity.
Low Density Parity Check(LDPC) Codes is a class of approaching limits error correction codes which has gained widely application in communications. The excellent performance, however, is the result of a large number of repeatedly conducting iterative decoding algorithm, and is apt to be seriously affected by small girth in the parity check matrix. In this paper we present a novel serial concatenated scheme for LDPC codes which utilize much smaller generation matrix and the interleaver to reduce possibilities of girth, thus reducing the number of iterations in decoding. Simulation shows that the new codes have better performance while less requirement of iterations.
In this paper, we construct the cyclic block-type low-density parity-check (CB-LDPC) codes for low complexity hardware implementation. The CB-LDPC code, which is a special class of quasi-cyclic LDPC (QC-LDPC), has an efficient encoding algorithm due to the simple structure of their parity-check matrices. A distribution of irregular parity-check matrix for the CB-LDPC is developed so that we can obtain an area-efficient decoder design, good error correction performance, and low complexity architecture implementation. The CB-LDPC code decoding uses the iterative min-sum algorithm (MSA) and the block parallel connection design to improve the hardware architecture complexity and area.
In this paper, a binary serial turbo LDPC code is presented. It represents a serial concatenated LDPC codes separated by interleavers, with iterative decoding. In this work, we aim to investigate the performance evaluation of concatenated code, with reduced complexity and decoding delay, associated with high order constellation using Gray mapping, over Gaussian and Rayleigh channels. Simulation results show that the performance of a serial concatenated LDPC codes is higher than that of single LDPC code with the same code rate and code block length.