At the end of 20 century,LDPC had already been on the research focus.While the LDPC became popular and the development of the computer technology,more and more decoders which were used at low-speed were implemented based on the software.Based on the analysis of relative discussion and research of primary decoding method of LDPC,aiming at the great market prospect of LDPC from now on,researching the distributing rule of the data in each cyclic submatrix during the process of initialization,horizontal operation and vertical operation,guaranteeing the program against the arithmetic which goes against the implementation on the computer,give an general-purpose efficient implementation on LDPC codes based on software.Ensuring the lost of BER is not evident,save time extraordinarily,and provide some idea for the FPGA implementation later.The method can be used to LDPC codes with different length and rate.According to the result of the test,on the same platform this method is faster than traditional method 4~5 times.This method shortens the time of research and enhances the efficiency.
At the end of 20 century,LDPC had already been on the research focus.While the LDPC became popular and the development of the computer technology,more and more decoders which were used at low-speed were implemented based on the software.Based on the analysis of relative discussion and research of primary decoding method of LDPC,aiming at the great market prospect of LDPC from now on,researching the distributing rule of the data in each cyclic submatrix during the process of initialization,horizontal operation and vertical operation,guaranteeing the program against the arithmetic which goes against the implementation on the computer,give an general-purpose efficient implementation on LDPC codes based on software.Ensuring the lost of BER is not evident,save time extraordinarily,and provide some idea for the FPGA implementation later.The method can be used to LDPC codes with different length and rate.According to the result of the test,on the same platform this method is faster than traditional method 4~5 times.This method shortens the time of research and enhances the efficiency.
At the beginning of 60's of last century,Gallager,the student of Shannon,issued the concept and a whole set of method for decoding of LDPC code at the first time in the world.But the LDPC code had not been on the focus of the research with its super performance until the end of the last century,for the improvement of the decoding theory and the development of the computer technology.Nowadays,the LDPC code is developing aiming at high speed and super performance.It studies the(8176,7154) LDPC code in the CCSDS near earth standard,aiming at the exigent demand of the high speed LDPC decoder.This method uses the character of the 1s to enhance the overlapped degree to improve the speed significantly of the decoder by the only change of the processing order of the CNU without any resource increase comparing with the traditional method.The decoder of the CCSDS near earth standard(8176,7154) LDPC code can save computation 10% by this method.And this implementation can also be used to other QC-LDPC codes.
After the introduction of iterative coding, Low Density Parity Check (LDPC) codes have received a lot of attention due to their remarkable near Shannon-limit performance and practical decoder implementation. However, when employing an LDPC code for various applications, multiple issues do arise at the simulation, algorithm and implementation levels. The first issue is the performance evaluation of the iterative LDPC decoder in the very low Bit Error Rate (BER) regions. So far, no analytical tool has been developed to evaluate the performance of LDPC codes. Unfortunately standard Monte Carlo (MC) simulations cannot be used for performance estimation in these low BER regions due to prohibitive execution times. The second issue is the efficiency of the decoding algorithm. Due to the presence of short cycles in the bipartite graph, sum-product decoding algorithms lead to considerable performance loss for short block-length LDPC codes and produce error floors for longer codes. In addition, the iterative processing and estimation of soft probabilistic values with these algorithms result in very high computational complexity, which in turn impedes the adoption of LDPC codes for power constrained systems. Another prime objective is to design a high throughput decoder architecture which is capable of supporting multiple rates and variable code lengths within minimal area.
This work aims to address and provide solutions to the above problems. As a solution to the performance estimation problem of LDPC codes, a highly efficient and novel fast BER simulation technique is developed. At the algorithm level, a performance improvement and error floor avoidance method is introduced, and a computationally efficient algorithm is developed for the sum-product decoding of LDPC codes. And finally, at the architecture level, a high throughput multi-rate variable code length implementation is presented which, when implemented, efficiently minimizes device resources while alleviating the routing complexity of the decoder.
Low-density parity-check (LDPC) codes have been shown to have good error correcting performance approaching Shannon’s limit. Good error correcting performance enables efficient and reliable communication. However, a LDPC code decoding algorithm needs to be executed efficiently to meet cost, time, power and bandwidth requirements of target applications. The constructed codes should also meet error rate performance requirements of those applications. Since their rediscovery, there has been much research work on LDPC code construction and implementation. LDPC codes can be designed over a wide space with parameters such as girth, rate and length. There is no unique method of constructing LDPC codes. Existing construction methods are limited in some way in producing good error correcting performing and easily implementable codes for a given rate and length. There is a need to develop methods of constructing codes over a wide range of rates and lengths with good performance and ease of hardware implementability. LDPC code hardware design and implementation depend on the structure of target LDPC code and is also as varied as LDPC matrix designs and constructions. There are several factors to be considered including decoding algorithm computations,processing nodes interconnection network, number of processing nodes, amount of memory, number of quantization bits and decoding delay. All of these issues can be handled in several different ways. \nThis thesis is about construction of LDPC codes and their hardware implementation. LDPC code construction and implementation issues mentioned above are too many to be addressed in one thesis. The main contribution of this thesis is the development of LDPC code construction methods for some classes of structured LDPC codes and techniques for reducing decoding time. We introduce two main methods for constructing structured codes. In the first method, column-weight two LDPC codes are derived from distance graphs. A wide range of girths, rates and lengths are obtained compared to existing methods. The performance and implementation complexity of obtained codes depends on the structure of their corresponding distance graphs. In the second method, a search algorithm based on bit-filing and progressive-edge growth algorithms is introduced for constructing quasi-cyclic LDPC codes. The algorithm can be used to form a distance or Tanner graph of a code. This method could also obtain codes over a wide range of parameters. Cycles of length four are avoided by observing the row-column constraint. \nRow-column connections observing this condition are searched sequentially or randomly. Although the girth conditions are not sufficient beyond six, larger girths codes were easily obtained especially at low rates. The advantage of this algorithm compared to other methods is its flexibility. It could be used to construct codes for a given rate and length with girths of at least six for any sub-matrix configuration or rearrangement. The code size is also easily varied by increasing or decreasing sub-matrix size. Codes obtained using a sequential search criteria show poor performance at low girths (6 and 8) while random searches result in good performing codes. \nQuasi-cyclic codes could be implemented in a variety of decoder architectures. One of the many options is the choice of processing nodes interconnect. We show how quasi-cyclic codes processing could be scheduled through a multistage network. Although these net-works have more delay than other modes of communication, they offer more flexibility at a reasonable cost. Banyan and Benes networks are suggested as the most suitable networks. \nDecoding delay is also one of several issues considered in decoder design and implementation. In this thesis, we overlap check and variable node computations to reduce decoding time. Three techniques are discussed, two of which are introduced in this thesis. The techniques are code matrix permutation, matrix space restriction and sub-matrix row-column scheduling. Matrix permutation rearranges the parity-check matrix such that rows and columns that do not have connections in common are separated. This techniques can be applied to any matrix. Its effectiveness largely depends on the structure of the code. We show that its success also depends on the size of row and column weights. Matrix space restriction is another technique that can be applied to any code and has fixed reduction in time or amount of overlap. Its success depends on the amount of restriction and may be traded with performance loss. The third technique already suggested in literature relies on the internal cyclic structure of sub-matrices to achieve overlapping. The technique is limited to LDPC code matrices in which the number of sub-matrices is equal to row and column weights. We show that it can be applied to other codes with a lager number of sub-matrices than code weights. However, in this case maximum overlap is not guaranteed. We calculate the lower bound on the amount of overlapping. Overlapping could be applied to any sub-matrix configuration of quasi-cyclic codes by arbitrarily choosing \nthe starting rows for processing. Overlapping decoding time depends on inter-iteration waiting times. We show that there are upper bounds on waiting times which depend on the code weights. Waiting times could be further reduced by restricting shifts in identity sub-matrices or using smaller sub-matrices. This overlapping technique can reduce the decoding time by up to 50% compared to conventional message and computation scheduling. \nTechniques of matrix permutation and space restriction results in decoder architectures that are flexible in LDPC code design in terms of code weights and size. This is due to the fact that with these techniques, rows and columns are processed in sequential order to achieve overlapping. However, in the existing technique, all sub-matrices have to be processed in parallel to achieve overlapping. Parallel processing of all code sub-matrices requires the architecture to have the number of processing units at least equal to the number sub-matrices. Processing units and memory space should therefore be distributed among the sub-matrices according to the sub-matrices arrangement. This leads to high complexity or inflexibility in the decoder architecture. We propose a simple, programmable and high throughput decoder architecture based on matrix permutation and space restriction techniques.
This paper presents an efficient general-purpose QC-LDPC decoder architecture by combining hardware with software.The proposed architecture can be applied to regular and irregular QC-LDPC codes of various rates,lengths and parity-check matrix structures,and supports min-sum approximation decoding algorithms and realizes different message passing scheduling strategies.Some complicated message update is implemented by a hardware accelerator,thus the decoding throughput is improved.According to the quasi-cyclic structure of the parity-check matrix,the messages are stored and processed by blocks in decoding.Parallel message processing can also be realized with a small increase in implementation complexity.
Low-density parity check (LDPC) codes have attracted the attention of a large number of researchers with its near-Shannon performance and easy implementation features. As a data coding scheme under the 5G scenario, how to achieve efficient encoding/decoding for LDPC codes has become one of the important research topics. Under this condition, this paper 1) proposes a novel decoding algorithm for LDPC codes using the Markov Chain Monte Carlo (MCMC) method and 2) introduces two improved versions, MCMC-S and MCMC-L, which achieve better results. Simulation figures show that the improved methods outperform the traditional belief propagation (BP) decoding method in relatively short codes by more than 1 dB at the bit error rate (BER) of 10-3. Very large scale integration (VLSI) architecture of the proposed method is also given in this paper.
Low-density parity-check (LDPC) codes are one of the most effective error controlling methods, which now are widely used in multiple communication systems, for example, DVB-S2, 802.16e, etc. In these communication standards, the adopted LDPC codes are all quasi-cyclic low-density parity-check (QC-LDPC) codes. The parity-check matrices of QC-LDPC codes consist of arrays of circulants, in which each row is the cyclic shift of the row above it, and the first row is the cyclic shift of the last row. This character of QC-LDPC codes results in the linear encoding complexity and opens the door for the multi-mode LDPC decoders with enough flexibility of resource multiplexing. Based on the quasi-cyclic character of QC-LDPC codes, a design method for multi-mode QC-LDPC decoders is proposed in this paper. The node memory is skillfully organized and can be expediently addressed by a simple control unit to save memory consumption in hardware implementation. Then this design method is implemented and test on Field Programmable Gate Array (FPGA) platform. The test results show that the resource occupied by the multi-mode decoder is only a little more than that of maximal resource occupied by the single-mode decoder, and this multi-mode decoder can support at least 3 code rates with the throughput higher than 100 Mbps when the iteration number is fixed to 12 and the clock frequency is set to 200 MHZ.