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Physical Review A

Robust surface code topology against sparse fabrication defects in a superconducting-qubit array

Yongchao Tang, Guo‐Xing Miao

Published Mar 15, 2016• 9 citations
Publisher

Abstract

Superconducting qubits arrays have become one of the most promising architectures for the practical implementation of universal quantum computing with quantum error correction codes. Here we propose a defect-tolerant surface code topology which is resistant to sparse fabrication defects. The topology is equivalent to a disk folded into $N$ layers. A physically defective qubit can be replaced with a working physical qubit within the same unit cell from a different layer. Thereby sparse fabrication errors can be collected into one sacrificial layer and isolated from the working layers by turning off their controllable couplers. We propose two schemes to realize this robust topology. One is to use flux qubits, and the other is based on Xmon qubits. A modified quantum circuit for the stabilization cycle of the Xmon qubits scheme is developed. We calculate and compare the per-operation error thresholds for these two schemes and find that the error threshold for the modified quantum circuit is close to that for the original stabilization cycle. A possible way to implement the intersecting connections between different Xmon qubits on the circuit level is also provided.

DOI
10.1103/physreva.93.032322

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Superconducting qubits arrays have become one of the most promising architectures for the practical implementation of universal quantum computing with quantum error correction codes. Here we propose a defect-tolerant surface code topology which is resistant to sparse fabrication defects. The topology is equivalent to a disk folded into NNN layers. A physically defective qubit can be replaced with a working physical qubit within the same unit cell from a different layer. Thereby sparse fabrication errors can be collected into one sacrificial layer and isolated from the working layers by turning off their controllable couplers. We propose two schemes to realize this robust topology. One is to use flux qubits, and the other is based on Xmon qubits. A modified quantum circuit for the stabilization cycle of the Xmon qubits scheme is developed. We calculate and compare the per-operation error thresholds for these two schemes and find that the error threshold for the modified quantum circuit is close to that for the original stabilization cycle. A possible way to implement the intersecting connections between different Xmon qubits on the circuit level is also provided.
The construction of topological error correction codes requires the ability to fabricate a lattice of physical qubits embedded on a manifold with a nontrivial topology such that the quantum information is encoded in the global degrees of freedom (i.e., the topology) of the manifold. However, the manufacturing of large-scale topological devices will undoubtedly suffer from fabrication errors---permanent faulty components such as missing physical qubits or failed entangling gates---introducing permanent defects into the topology of the lattice and hence significantly reducing the distance of the code and the quality of the encoded logical qubits. In this work we investigate how fabrication errors affect the performance of topological codes, using the surface code as the test bed. A known approach to mitigate defective lattices involves the use of primitive swap gates in a long sequence of syndrome extraction circuits. Instead, we show that in the presence of fabrication errors the syndrome can be determined using the supercheck operator approach and the outcome of the defective gauge stabilizer generators without any additional computational overhead or use of swap gates. We report numerical fault-tolerance thresholds in the presence of both qubit fabrication and gate fabrication errors using a circuit-based noise model and the minimum-weight perfect-matching decoder. Our numerical analysis is most applicable to two-dimensional chip-based technologies, but the techniques presented here can be readily extended to other topological architectures. We find that in the presence of 88%8 qubit fabrication errors, the surface code can still tolerate a computational error rate of up to 0.10.1%0.1.
We present a scalable scheme for executing the error-correction cycle of a monolithic surface-code fabric composed of fast-flux-tuneable transmon qubits with nearest-neighbor coupling. An eight-qubit unit cell forms the basis for repeating both the quantum hardware and coherent control, enabling spatial multiplexing. This control uses three fixed frequencies for all single-qubit gates and a unique frequency detuning pattern for each qubit in the cell. By pipelining the interaction and readout steps of ancilla-based X- and Z-type stabilizer measurements, we can engineer detuning patterns that avoid all second-order transmon-transmon interactions except those exploited in controlled-phase gates, regardless of fabric size. Our scheme is applicable to defect-based and planar logical qubits, including lattice surgery.
A solid-state quantum-computing architecture will require the fabrication of arrays of many coupled qubits. It is inevitable that this process will produce qubits and couplers with varying performance, with some components underperforming due to imperfect fabrication. Quantum error-correction requires high-performing components and hence these defects must be dealt with, either by adapting the code to exclude the defects, or by informing the decoder to accommodate defects in post-processing. Here we implement and compare strategies to operate distance-5 surface codes on a quantum processor consisting of a square-lattice array of 120 superconducting qubits. We demonstrate a dramatic reduction in the probability of a logical error in a memory experiment by excluding underperforming components, compared with both a standard approach of ignoring defects, and a defect-aware decoding approach. We observe up to 2.8X improvement in logical errors per round when excluding defects compared with the standard defect-ignorant approach (1.62% compared to 4.49%). In contrast, defect-aware decoding gives only modest gains. Defects are also expected to be particularly harmful for measurement-based logical operations. Using a stability experiment we show that excluding defects resurrects measurement-based logic gate performance, observing a 6.3% per-round suppression of failure rate when excluding defects, compared to zero suppression otherwise. Furthermore, we show a further substantial decrease in logical errors when using leakage post-selection in combination with our defect exclusion strategies, resulting in a distance-5 code outperforming the best distance-3 in one basis. Our experiments therefore give a proof-of-principle demonstration of the essential utility of defect exclusion methods in the scale-up of solid-state quantum computing approaches.
Superconducting qubits, while promising for scalability and long coherence times, contain more than two energy levels, and therefore are susceptible to errors generated by the leakage of population outside of the computational subspace. Such leakage errors constitute a prominent roadblock towards fault-tolerant quantum computing (FTQC) with superconducting qubits. FTQC using topological codes is based on sequential measurements of multiqubit stabilizer operators. Here, we first propose a leakage-resilient procedure to perform repetitive measurements of multiqubit stabilizer operators, and then use this scheme as an ingredient to develop a leakage-resilient approach for surface code quantum error correction with superconducting circuits. Our protocol is based on swap operations between data and ancilla qubits at the end of every cycle, requiring read-out and reset operations on every physical qubit in the system, and thereby preventing persistent leakage errors from occurring.
When implementing scalable fault-tolerant quantum computing using superconducting quantum processors, one of the critical challenges to overcome is the presence of defective qubits arising from fabrication and calibration imperfections. A defect on a specific qubit severely restricts the connectivity between adjacent qubits, disrupts stabilizer measurements, induces frequent detection events, and consequently inflates the logical error rate. To mitigate this issue, various strategies have been proposed, such as syndrome extraction circuits based on stabilizer folding and the construction of super-stabilizers via gauge operators. However, these methods have primarily been developed for architectures with relatively high connectivity of 3 to 4. Furthermore, experimental demonstrations showing an actual reduction in logical error rates in the presence of physical hardware defects have been lacking. In this work, we propose a defect-avoidance scheme tailored for the heavy-hexagon architecture, which features a lower connectivity of 2 to 3. While previous approaches required four measurement cycles to measure all gauge operators comprising a super-stabilizer, our proposed scheme completes all gauge measurements within only two cycles. We experimentally validate this approach on IBM quantum hardware by identifying physical defects and implementing the defect-avoidance circuits. As a result, avoiding the defect yields an approximately 10\% reduction in the logical error rate per cycle for both logical XXX and ZZZ errors. These findings demonstrate that defects in superconducting hardware can be successfully handled even under the constrained connectivity of heavy-hexagon lattices, and that defect avoidance substantially reduces logical errors on real quantum hardware.
Quantum error correction is a crucial technology for fault tolerant quantum computing. On superconducting platforms, hardware defects in large scale quantum processors can disrupt the regular lattice structure of topological codes and impair their error correction capabilities. Although defect adaptive methods for surface codes have been extensively studied, other topological codes such as color codes still lack a systematic framework for handling defects. To address this issue, we propose a universal superstabilizer scheme applicable to data qubit defects in arbitrary stabilizer codes. Based on this scheme, we develop concrete repair methods for isolated defects of both internal data qubits and ancilla qubits in color codes defined on square lattices. Furthermore, for ancilla qubit defects, we present two optimization schemes. One scheme reuses neighboring ancilla qubits, and the other employs iSWAP gates. Unlike conventional approaches that directly disable neighboring data qubits and thus cause resource waste, both of our schemes avoid such waste and consequently achieve a lower logical error rate.Integrating the above techniques, we construct a comprehensive defect adaptive architecture for color codes to handle various defect clusters. We also show that our scheme supports a full transversal Clifford gate set and lattice surgery operations. These results provide a systematic theoretical pathway for deploying robust and low overhead color codes on defective quantum hardware.