The construction of topological error correction codes requires the ability to fabricate a lattice of physical qubits embedded on a manifold with a nontrivial topology such that the quantum information is encoded in the global degrees of freedom (i.e., the topology) of the manifold. However, the manufacturing of large-scale topological devices will undoubtedly suffer from fabrication errors---permanent faulty components such as missing physical qubits or failed entangling gates---introducing permanent defects into the topology of the lattice and hence significantly reducing the distance of the code and the quality of the encoded logical qubits. In this work we investigate how fabrication errors affect the performance of topological codes, using the surface code as the test bed. A known approach to mitigate defective lattices involves the use of primitive swap gates in a long sequence of syndrome extraction circuits. Instead, we show that in the presence of fabrication errors the syndrome can be determined using the supercheck operator approach and the outcome of the defective gauge stabilizer generators without any additional computational overhead or use of swap gates. We report numerical fault-tolerance thresholds in the presence of both qubit fabrication and gate fabrication errors using a circuit-based noise model and the minimum-weight perfect-matching decoder. Our numerical analysis is most applicable to two-dimensional chip-based technologies, but the techniques presented here can be readily extended to other topological architectures. We find that in the presence of $8%$ qubit fabrication errors, the surface code can still tolerate a computational error rate of up to $0.1%$.
The construction of topological error correction codes requires the ability to fabricate a lattice of physical qubits embedded on a manifold with a nontrivial topology such that the quantum information is encoded in the global degrees of freedom (i.e., the topology) of the manifold. However, the manufacturing of large-scale topological devices will undoubtedly suffer from fabrication errors---permanent faulty components such as missing physical qubits or failed entangling gates---introducing permanent defects into the topology of the lattice and hence significantly reducing the distance of the code and the quality of the encoded logical qubits. In this work we investigate how fabrication errors affect the performance of topological codes, using the surface code as the test bed. A known approach to mitigate defective lattices involves the use of primitive swap gates in a long sequence of syndrome extraction circuits. Instead, we show that in the presence of fabrication errors the syndrome can be determined using the supercheck operator approach and the outcome of the defective gauge stabilizer generators without any additional computational overhead or use of swap gates. We report numerical fault-tolerance thresholds in the presence of both qubit fabrication and gate fabrication errors using a circuit-based noise model and the minimum-weight perfect-matching decoder. Our numerical analysis is most applicable to two-dimensional chip-based technologies, but the techniques presented here can be readily extended to other topological architectures. We find that in the presence of 8 qubit fabrication errors, the surface code can still tolerate a computational error rate of up to 0.1.
The yield of physical qubits fabricated in the laboratory is much lower than that of classical transistors in production semiconductor fabrication. Actual implementations of quantum computers will be susceptible to loss in the form of physically faulty qubits. Though these physical faults must negatively affect the computation, we can deal with them by adapting error-correction schemes. In this paper we have simulated statically placed single-fault lattices and lattices with randomly placed faults at functional qubit yields of 80%, 90%, and 95%, showing practical performance of a defective surface code by employing actual circuit constructions and realistic errors on every gate, including identity gates. We extend Stace et al 's superplaquettes solution against dynamic losses for the surface code to handle static losses such as physically faulty qubits [ 1 ]. The single-fault analysis shows that a static loss at the periphery of the lattice has less negative effect than a static loss at the center. The randomly faulty analysis shows that 95% yield is good enough to build a large-scale quantum computer. The local gate error rate threshold is , and a code distance of seven suppresses the residual error rate below the original error rate at . 90% yield is also good enough when we discard badly fabricated quantum computation chips, while 80% yield does not show enough error suppression even when discarding 90% of the chips. We evaluated several metrics for predicting chip performance, and found that the average of the product of the number of data qubits and the cycle time of a stabilizer measurement of stabilizers gave the strongest correlation with logical error rates. Our analysis will help with selecting usable quantum computation chips from among the pool of all fabricated chips.
Quantum error correction (QEC) represents a critical enabler for fault-tolerant quantum computing, protecting fragile quantum states from decoherence and operational errors. This paper provides a comprehensive analysis of leading quantum error correction schemes, focusing on surface codes and topological codes within the context of Noisy Intermediate-Scale Quantum (NISQ) era processors. We examine the theoretical foundations of stabilizer codes, compare surface code implementations with code distances ranging from d=3 to d=17, and analyze topological codes including toric codes and color codes. Our investigation encompasses syndrome extraction circuits, logical qubit encoding strategies, and threshold analysis for contemporary quantum hardware platforms. Performance metrics reveal that surface codes achieve error thresholds of approximately 1% with realistic noise models, while topological codes offer architectural advantages for specific qubit connectivity constraints. We discuss implementation challenges on current NISQ processors including IBM Quantum, Google Sycamore, and IonQ systems, addressing qubit overhead, gate fidelity requirements, and decoding algorithms. This analysis provides insights for selecting appropriate error correction schemes based on application requirements and hardware capabilities.
In this thesis, we consider steps towards building a useful quantum computer in the presence of realistic errors. We start by presenting a novel scheme for fault-tolerant quantum computation with Rydberg atoms. The scheme uses topological error correction codes to provide fault-tolerance and utilises electromagnetically induced transparency to perform entangling gates between qubits. We examine the benefits of this scheme compared to alternative approaches, and we investigate the errors that are likely to occur and how these can be managed. We then consider how to perform quantum computation with a surface code based quantum computer that has permanently faulty components. We study both faulty links between qubits, which prevent qubits from interacting, and faulty qubits themselves; such faults could affect a wide variety of physical implementations, including schemes that use superconducting qubits and those that use trapped ions. The approach we propose for dealing with these faulty components requires minimal modification to the quantum operations required by the surface code and should therefore be implementable by almost all current and future proposals for surface code based quantum devices. Finally, we consider how to perform fault-tolerant quantum computation with components that fail probabilistically. This section is largely motivated by quantum computation with linear optics and therefore focuses on quantum computation with cluster states. We show that these probabilistic failures can be tolerated providing the failure rate is suitably low, and we present methods for increasing error thresholds in the presence of such errors.
Topological codes have many desirable properties that allow fault-tolerant quantum computation with relatively low overhead. A core challenge for these codes, however, is to achieve a low-overhead universal gate set with limited connectivity. In this work, we explore a non-Pauli stabilizer code that can be used to complete a universal gate set on topological toric and surface codes in strictly two dimensions. Fault-tolerant syndrome extraction for the non-Pauli code requires mid-circuit X corrections, a key difference to conventional Pauli codes. We construct and benchmark a just-in-time (JIT) matching decoder to reliably decide these corrections. Under a phenomenological error model with equally likely physical and measurement errors, we find a high threshold of ≈2.5%, close to the ≈2.9% of a decoder with access to the full syndrome history. We also perform a finite-size scaling analysis to estimate how the logical error rate scales below threshold and verify an exponential suppression in both physical error rate and in the system size. A second global decoding step for Z errors is required and the non-Clifford gates in the circuit reduce the threshold from ≈2.9% to ≈1.8% with a naive decoder. We show how Z decoding can be improved using knowledge of the X corrections, pushing the threshold to ≈2.2%. Our results suggest non-Clifford logic in 2D codes could perform comparably to 2D quantum memory. Our formalism for efficient benchmarking and decoding directly generalizes to a broader family of CSS codes whose X stabilizers are twisted by diagonal Clifford operators, and spacetime versions thereof, defined by CSS-like circuits enriched by CCZ, CS, and T gates.
Quantum computers are far more error-prone than their classical counterparts. Therefore, to build a quantum computer capable of running large-scale quantum algorithms, we must use the techniques of quantum error correction to ensure that the computer produces the correct output even when its components are unreliable. However, the resource requirements of building such a fault-tolerant quantum computer are currently prohibitive. Here, we examine the utility of using three-dimensional (3D) surface codes in a fault-tolerant quantum computer. This family of topological error-correcting codes is a generalization of the well-known 2D surface code to three spatial dimensions. We show that certain 3D surface codes have a transversal logical non-Clifford gate. In a quantum computing architecture, a non-Clifford gate is required to achieve computational universality. Transversal gates do not entangle qubits in different codes, so they are naturally fault tolerant because they do not spread errors. Next, we consider the problem of decoding 3D surface codes. In a quantum error-correcting code, we cannot observe the qubits directly, so we measure parity-check operators to gain information about the state of the code. Decoding is the problem of estimating what error has occurred given a list of unsatisfied parity checks. We observe that 3D surface codes offer asymmetric protection against bit-flip and phase-flip errors, but in both cases, we find that a threshold error rate exists below which we can suppress logical errors by increasing the size of the code. We use our results about logical gates and decoding to propose two fault-tolerant quantum computing architectures that utilize 3D surface codes. Finally, we compare the resource requirements of our architectures with the requirements of leading quantum computing architectures based on topological codes. We find that one of our architectures may be competitive with the leading architectures, depending on the properties of the physical systems used to build the qubits.