Besides serving as promising candidates for realizing quantum computing, superconducting quantum circuits are one of a few macroscopic physical systems in which fundamental quantum phenomena can be directly demonstrated and tested, giving rise to a vast field of intensive research work both theoretically and experimentally. In this paper we report our work on the fabrication of superconducting quantum circuits, starting from its building blocks: Al/AlO x /Al Josephson junctions. By using electron beam lithography patterning and shadow evaporation, we have fabricated aluminum Josephson junctions with a controllable critical current density ( j c ) and wide range of junction sizes from 0.01 μm 2 up to 1 μm 2 . We have carried out systematical studies on the oxidation process in fabricating Al/AlO x /Al Josephson junctions suitable for superconducting flux qubits. Furthermore, we have also fabricated superconducting quantum circuits such as superconducting flux qubits and charge-flux qubits.
One of the practical limitations of solid-state superconducting quantum processors is the collision of the qubit resonance frequencies, caused by their deviation from the design specifications due to the low reproducibility in qubit fabrication. Josephson junction 100 nm-scale nonlinear inductance of the qubits still suffers from Dolan-bridge shadow evaporation process. Here, we report on a robust wafer-scale Al/AlOx/Al Dolan-bridge Josephson junction (JJ) process using preliminary shadow evaporation bias resist mask correction and comprehensive oxidation optimization. We introduce a topology correction model for two-layer resist mask biasing at a wafer-scale, which takes into account an evaporation source geometry. It results in Josephson junction area variation coefficient (
CVA ) improvement down to 1.1% for the critical dimensions from 130 × 170 nm2 to 130 × 670 nm2 over 70 × 70 mm2 (49 cm2) wafer working area. Next, we investigate JJ oxidation process (oxidation method, pressure and time) and its impact on the room temperature resistance reproducibility. Finally, we combine both shadow evaporation bias correction and oxidation best practices for 4-inch wafers, improving
CVRN down to 6.0/5.2/4.1% for 0.025 µm2 JJ area and 4.0/3.4/2.3% for 0.090 µm2 JJ area for 49/25/16 cm2 wafer working area correspondingly. The proposed model and oxidation method can be useful for robust wafer-scale superconducting quantum processors fabrication.
The most commonly used physical realization of superconducting qubits for quantum circuits is a transmon. There are a number of superconducting quantum circuits applications, where Josephson junction critical current reproducibility over a chip is crucial. Here, we report on a robust chip scale
Al/AlOx/Al junctions fabrication method due to comprehensive study of shadow evaporation and oxidation steps. We experimentally demonstrate the evidence of optimal Josephson junction electrodes thickness, deposition rate and deposition angle, which ensure minimal electrode surface and line edge roughness. The influence of oxidation method, pressure and time on critical current reproducibility is determined. With the proposed method we demonstrate
Al/AlOx/Al junction fabrication with the critical current variation (
σ/Ic) less than 3.9% (from
150×200 to
150×600 nm2 area) and 7.7% (for
100×100 nm2 area) over
20×20 mm2 chip. Finally, we fabricate separately three
5×10 mm2 chips with 18 transmon qubits (near 4.3 GHz frequency) showing less than 1.9% frequency variation between qubit on different chips. The proposed approach and optimization criteria can be utilized for a robust wafer-scale superconducting qubit circuits fabrication.