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Bulletin of the American Physical Society

Shadow Evaporated Josephson Junctions for superconducting qubits

Fabio Altomare, Jos 'e Aumentado, Kevin D. Osborn, Joshua Strong, Raymond W. Simmonds

Published Mar 7, 2007• 0 citations
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One of the practical limitations of solid-state superconducting quantum processors is the collision of the qubit resonance frequencies, caused by their deviation from the design specifications due to the low reproducibility in qubit fabrication. Josephson junction 100 nm-scale nonlinear inductance of the qubits still suffers from Dolan-bridge shadow evaporation process. Here, we report on a robust wafer-scale Al/AlOx/Al Dolan-bridge Josephson junction (JJ) process using preliminary shadow evaporation bias resist mask correction and comprehensive oxidation optimization. We introduce a topology correction model for two-layer resist mask biasing at a wafer-scale, which takes into account an evaporation source geometry. It results in Josephson junction area variation coefficient ( $$\:{CV}_{A}$$ ) improvement down to 1.1% for the critical dimensions from 130 × 170 nm2 to 130 × 670 nm2 over 70 × 70 mm2 (49 cm2) wafer working area. Next, we investigate JJ oxidation process (oxidation method, pressure and time) and its impact on the room temperature resistance reproducibility. Finally, we combine both shadow evaporation bias correction and oxidation best practices for 4-inch wafers, improving $$\:{CV}_{{R}_{N}}$$ down to 6.0/5.2/4.1% for 0.025 µm2 JJ area and 4.0/3.4/2.3% for 0.090 µm2 JJ area for 49/25/16 cm2 wafer working area correspondingly. The proposed model and oxidation method can be useful for robust wafer-scale superconducting quantum processors fabrication.

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Abstract The uniformity of Josephson-junction (JJ) characteristics is crucial in wafer-scale superconducting quantum-bit (qubit) integration. To achieve the level of accuracy demanded the circuits, every detail of the fabrication process needs to be optimized. Here we reveal that the junction-resistance (R N) variations of Al/AlO x /Al JJs are affected by the metal deposition on the sidewall of the resist mask during shadow evaporation. The effect is reproduced in numerical simulation using a simple model taking into account the resist structure and the evaporation angle. To overcome the issue, we introduce a two-step shadow evaporation method to reduce the variation of R N. As a result, the coefficient of variations across a 3-inch wafer decreases from 6.7% to 4.5%, achieving 1.1% in a chip with an area of 10 mm × 10 mm. This method is promising for developing large-scale superconducting quantum computers.

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One of the practical limitations of solid-state superconducting quantum processors is the collision of the qubit resonance frequencies, caused by their deviation from the design specifications due to the low reproducibility in qubit fabrication. Josephson junction 100 nm-scale nonlinear inductance of the qubits still suffers from Dolan-bridge shadow evaporation process. Here, we report on a robust wafer-scale Al/AlOx/Al Dolan-bridge Josephson junction (JJ) process using preliminary shadow evaporation bias resist mask correction and comprehensive oxidation optimization. We introduce a topology correction model for two-layer resist mask biasing at a wafer-scale, which takes into account an evaporation source geometry. It results in Josephson junction area variation coefficient (  CVA\:{CV}_{A}CVA​ ) improvement down to 1.1% for the critical dimensions from 130 × 170 nm2 to 130 × 670 nm2 over 70 × 70 mm2 (49 cm2) wafer working area. Next, we investigate JJ oxidation process (oxidation method, pressure and time) and its impact on the room temperature resistance reproducibility. Finally, we combine both shadow evaporation bias correction and oxidation best practices for 4-inch wafers, improving  CVRN\:{CV}_{{R}_{N}}CVRN​​ down to 6.0/5.2/4.1% for 0.025 µm2 JJ area and 4.0/3.4/2.3% for 0.090 µm2 JJ area for 49/25/16 cm2 wafer working area correspondingly. The proposed model and oxidation method can be useful for robust wafer-scale superconducting quantum processors fabrication.
Abstract The uniformity of Josephson-junction (JJ) characteristics is crucial in wafer-scale superconducting quantum-bit (qubit) integration. To achieve the level of accuracy demanded the circuits, every detail of the fabrication process needs to be optimized. Here we reveal that the junction-resistance (R N) variations of Al/AlO x /Al JJs are affected by the metal deposition on the sidewall of the resist mask during shadow evaporation. The effect is reproduced in numerical simulation using a simple model taking into account the resist structure and the evaporation angle. To overcome the issue, we introduce a two-step shadow evaporation method to reduce the variation of R N. As a result, the coefficient of variations across a 3-inch wafer decreases from 6.7% to 4.5%, achieving 1.1% in a chip with an area of 10 mm × 10 mm. This method is promising for developing large-scale superconducting quantum computers.