We have developed a single-flux-quantum (SFQ) read only memory (ROM) cell. The developed SFQ ROM cell has compatibility with an existing cell library. It comprises splitters and confluence buffers. For large integration, we have merged two 1-bit cells into one cell with peripheral elements, and we have optimized circuit parameters with an automatic optimization tool. The cell area is approximately 50% of our preliminary SFQ sequential ROM cell using the CONNECT cell library. A test circuit was fabricated using a 25 μA/ μm2Nb integration process. We have confirmed correct operation for all six I/O ports. The measured bias margins were almost the same magnitude as the simulation result.
We have developed a single-flux-quantum (SFQ) read only memory (ROM) cell. The developed SFQ ROM cell has compatibility with an existing cell library. It comprises splitters and confluence buffers. For large integration, we have merged two 1-bit cells into one cell with peripheral elements, and we have optimized circuit parameters with an automatic optimization tool. The cell area is approximately 50% of our preliminary SFQ sequential ROM cell using the CONNECT cell library. A test circuit was fabricated using a 25 μA/ μm2Nb integration process. We have confirmed correct operation for all six I/O ports. The measured bias margins were almost the same magnitude as the simulation result.
We have developed a cell library for superconducting large scale integrated (LSI) digital circuits based on Single Flux Quantum (SFQ) devices. The circuits were designed for a 6-kA/cm2Nb/AlOx/Nb junction process with 10 mask levels including one ground plane and two Nb wiring layers. The initial design and optimization of the circuit parameters were achieved by means of the optimization functions in a circuit simulator, PSCAN2, to ensure that important circuit parameters, Josephson critical current (IC), bias current (Ibias), and inductance satisfied minimal margin requirements. Critical margins of ICand Ibiaswere then further improved manually. To compensate the scattering in the circuit parameters from fabrication by design as much as possible, the critical junction parameters were optimized to further centralize the IC. The library cells were laid out following our design rules determined by systematic experiments on process control monitors (PCM). Basic cells including Josephson transmission lines, splitters, confluence buffers, D flip-flops, T flip-flops, and XOR and NDRO gates were designed, fabricated, and successfully tested at low frequencies. Wide overlaps of the operating regions for the common bias voltages were confirmed.
We present a superconducting single-flux-quantum (SFQ) mask ROM comprising 2-bit storage cells and a sequential-access driver. Four types of storage cells for 2-bit data (“00,” “10,” “01,” “11”) are adopted for reduction of the cell dimensions, whereas the sequential access is suitable for a single-chip quantum voltage waveform generator implemented with an SFQ-based digital-to-analog converter. 2-bit storage cells of 60 × 70 µm2 are fabricated using a niobium integration technology and tested in liquid helium. Operation of a sequential-access mask ROM with data of 8 bits × 6 words is also demonstrated.
ENGLISH ABSTRACT: Rapid Single Flux Quantum (RSFQ) cells are key in the design of complex and applicable RSFQ electronic circuits. These cells are low-level circuit elements that are used repeatedly to build larger, applicable RSFQ circuitry. Making these cells simple to layout and manufacture, but reliable for extensive use demands a careful development process for RSFQ cells. Cell functionality is verified through simulations, thereafter the cell is laid out in special software packages. Inductance of on-chip superconductor structures is extracted through careful modelling with numerical field solver software. A cell library has been developed by incorporating existing or published cells after further analysis and optimization, as well as developing new cells. Cells that have been adapted into the library include the Josephson transmission line (JTL), Splitter, Merger, D-Flip Flop (DFF), T-Flip Flop (TFF), NOT, AND, OR and XOR, DC-SFQ and SFQ-DC and PTL Driver and Receivers. New cells include NOR, NAND and XNOR. The cells were designed for the IPHT’s RSFQ1D 1kA/cmª and Hypres’ 4.5kA/cmª processes. The cells in the library have good bias current operating margins obtained through simulations (> ±26%). All cells have all the parameters listed in the thesis including extracted inductance values. In order to have a complete and verified RSFQ cell library, cells have been sent for fabrication at IPHT and Hypres facilities. These cells can now be tested on-chip, in the laboratory, to establish functionality and practical bias current margins. All test signal patterns and bias currents required for testing are defined to allow co-workers or collaborators to test the cells.
Rapid Single flux quantum (RSFQ) confluence buffer is widely used in complex superconductive digital circuits. In this work, we have improved the currently used confluence buffer and obtained a more soundly designed confluence buffer. In simulations, improvements in the bias margins of 11 % and the global margins of 10%, compared to the previously used confluence buffer, were achieved. Global margins are very important in estimating a process error range allowed in fabrications. We used two circuit simulation tools, WRspice and Julia, to design and optimize the confluence buffer. We used Xic to obtain a mask layout. We fabricated the improved circuits by using Nb technology. The test results at low frequency showed that the improved confluence buffer operated correctly and had a very wide main bias margin of +/-43% enhanced from +/-26% of the previously used confluence buffer.
A single flux quantum (SFQ) logic cell library has been developed for the 10kA/cm2 Nb multi-layer fabrication process to efficiently design large-scale SFQ digital circuits. In the new cell library, the critical current density of Josephson junctions is increased from 2.5kA/cm2 to 10kA/cm2 compared to our conventional cell library, and the McCumber-Stwart parameter of each Josephson junction is increased to 2 in order to increase the circuit operation speed. More than 300 cells have been designed, including fundamental logic cells and wiring cells for passive interconnects. We have measured all cells and confirmed they stably operate with wide operating margins. On-chip high-speed test of the toggle flip-flop (TFF) cell has been performed by measuring the input and output voltages. The TFF cell at the input frequency of up to 400GHz was confirmed to operate correctly. Also, several fundamental digital circuits, a 4-bit concurrent-flow shift register and a bit-serial adder have been designed using the new cell library, and the correct operations of the circuits have been demonstrated at high clock frequencies of more than 100GHz.
A new design concept for the Josephson-junction random access memory (RAM) has been developed. In contrast to previous RAMs based on single flux quantization (SFQ), in our system READ and WRITE operations employ ballistic transfer of SFQ pulses along bit lines (either Josephson transmission lines, or passive superconducting microstrip lines, or their combination). The basic memory cells are the single-junction SQUIDs, connected serially by the bit lines and inductively coupled to word lines. READ and WRITE operations are performed by sending SFQ pulses in appropriate directions along bit lines, and DC currents of appropriate polarity into word lines. This approach allows design of very dense memories with n/spl les/2 Josephson junctions per bit, memory cell area smaller than 80 /spl lambda//sup 2/ (where /spl lambda/ is the minimum feature size), and the critical parameter margin well above /spl plusmn/20%. In this paper we present the general structure of the RSFQ RAM, as well as design and results of testing of the basic memory cell and decoder circuitry using Hypres' 3.5-/spl mu/m, 1-kA/cm/sup 2/ Nb-trilayer technology.>