I Abstract -- As the integration level of superconducting digital circuits increases, flux trapping in these devices becomes a serious problem. High resolution A/D converters and other high speed signal processing systems have been demonstrated with junction counts well into the lo3 range. Such large circuits require special testing techniques to prevent flux trapping within the gates, which can reduce bias margins and cause malfunctions of these devices. We discuss the results of experiments using single flux quantum shift registers in which we have varied the ground plane hole pattern and magnetic shield degaussing procedure to minimize flux trapping in these circuits. The operating bias margins of the shift registers have been measured as a function of different testing procedures and ground plane hole designs. In situ degaussing of the magnetic shields aids in the reduction of flux trapping and gave the best results. Measurements of the permeability of mu metal at 4.2 K are discussed.
I Abstract -- As the integration level of superconducting digital circuits increases, flux trapping in these devices becomes a serious problem. High resolution A/D converters and other high speed signal processing systems have been demonstrated with junction counts well into the lo3 range. Such large circuits require special testing techniques to prevent flux trapping within the gates, which can reduce bias margins and cause malfunctions of these devices. We discuss the results of experiments using single flux quantum shift registers in which we have varied the ground plane hole pattern and magnetic shield degaussing procedure to minimize flux trapping in these circuits. The operating bias margins of the shift registers have been measured as a function of different testing procedures and ground plane hole designs. In situ degaussing of the magnetic shields aids in the reduction of flux trapping and gave the best results. Measurements of the permeability of mu metal at 4.2 K are discussed.
As the integration level of superconducting digital circuits increases, flux trapping in these devices becomes a serious problem. High resolution A/D converters and other high speed signal processing systems have been demonstrated with junction counts well into the 10/sup 3/ range. Such large circuits require special testing techniques to prevent flux trapping within the gates, which can reduce bias margins and cause malfunctions of these devices. We discuss the results of experiments using single flux quantum shift registers in which we have varied the ground plane hole pattern and magnetic shield degaussing procedure to minimize flux trapping in these circuits. The operating bias margins of the shift registers have been measured as a function of different testing procedures and ground plane hole designs. In situ degaussing of the magnetic shields aids in the reduction of flux trapping and gave the best results. Measurements of the permeability of mu metal at 4.2 K are discussed.
A variety of superconductor integrated circuits composed of six ac-powered SFQ shift registers with a total of 27078 bits and 108500 Josephson junctions (JJs) per 5 mm × 5 mm chip have been designed, fabricated, and tested to characterize flux trapping, fabrication process yield, and parameter spread. The six 4513-bit registers in the circuits have a common single-phase ac clock and individual input/output drivers, allowing for their parallel testing. We have investigated flux trapping in the circuits with various geometry, size, distance between moats in active ground planes (GPs), and containing up to three additional ‘dummy’ GPs, using multiple cooldowns through the critical temperature with various cooling rates and residual magnetic fields up to ∼ 1.2 µT. For the slit-type and square moats arrayed along the sides of the register cells, we have found a negligible effect of flux sequestered in the moats on the operating margins of the registers, and a negligible probability of detrimental flux trapping outside of the moats. Circuits with 0.3-µm-wide slit moats occupying less than 2% of the circuit area were fully operational in 100% of cooldowns, supporting the viability of a very large-scale integration of superconductor digital circuits. We have also found a strong enhancement of flux trapping outside the moats in circuits with closely spaced GPs and determined a critical distance,${{{\boldsymbol{t}}}_{\boldsymbol{c}}} \approx $0.6 µm, between them. The presence of two or more GPs spaced below thetcrendered the circuits nonoperational in 100% of cooldowns. We have measured 30 chips with over 3M JJs and determined individual cell operating margins in 138 registers to characterize the fabrication-related parameter spread and detect fabrication defects and flux-trapping events. By finding outlier bit-cells in the statistical distribution of the individual cell margins, we detected about one fabrication defect per million JJs, in most cases causing magnetic flux trapping in the affected cell.The circuits have been fabricated in the SFQ5ee fabrication process at MIT Lincoln Laboratory (MIT LL).
We diagnosed circuits to identify of margin reduction mechanisms in large-scale SFQ circuits. Two types of shift registers with partial or full bias line shields were designed and tested. We investigated the locations and origins of circuit errors by measuring bias margins and output waveforms. The results indicated that bias line currents can degrade the bias margin around the periphery in large-scale circuits with partial bias line shields. On the other hand, no apparent reduction of bias margins was observed in any part of the circuit area in the circuits with full bias line shields. However, we observed a reduction of the bias margin due to flux trapping even when we used a completely non-magnetic He dewar surrounded by a dual-layer permalloy metal shield. We found that the probability of finding a defect in a circuit with 10,000 Josephson junctions is less than 60%.
Abstract We report the design and test of reciprocal quantum logic shift-register yield vehicles consisting of up to 72 800 Josephson junction devices per die, the largest digital superconducting circuits ever reported. Multiple physical layout styles were matched to the MIT Lincoln Laboratory foundry, which supports processes with both four and eight metal layers and minimum feature size of 0.5 μ m. The largest individual circuits with 40 400 junctions indicate large operating margins of ±20% on ac clock amplitude. In one case the data were reproducible to the accuracy of the measurement, ±1% across five thermal cycles using only the rudimentary precautions of passive mu-metal magnetic shielding and a controlled cool-down rate of 3 mK s −1 in the test fixture. We conclude that with proper mitigation techniques, flux-trapping is no longer a limiting consideration for very-large-scale-integration of superconductor digital logic.
Moats in superconducting ground planes are used to trap magnetic flux away from sensitive parts of superconductor integrated circuits. We simulate the effect of magnetic flux trapped in moats on the operating margins of ac-biased SFQ shift registers (ShReg) with two ground planes for various congruent moat geometries, moat sizes, locations in the ShReg cells, number and polarity of the trapped fluxons. Using inductance extractor InductEx, we extract mutual couplings between the moats and the ShReg inductors and include them in the refined netlist. Then we use JoSim to simulate the circuit operation and find the threshold ac clock amplitude above which the register starts to operate correctly. The relative change in this threshold is used to characterize the influence of flux trapping on the circuit operation. Monte-Carlo simulations are used to investigate the effect of the circuit parameter variations on the statistics of the threshold, using the standard deviation of the Josephson junction critical current and of the circuit inductance extracted from the fabrication process control monitors. The obtained distributions are compared with the independently measured distributions of the threshold amplitude for the individual cells of an ac-biased shift registers with 108,500 Josephson junctions. The results show that flux trapping in properly designed moats has a very small effect on the operation margins of the large-scale shift registers, whereas the main contribution to the cell-to-cell variation of the threshold comes from the variation of the junctions’ critical currents.
We develop an ac-biased shift register introduced in our previous work (V. K. Semenov et al., IEEE Trans. Appl. Supercond., vol. 25, no. 3, 1301507, June 2015) into a benchmark circuit for evaluation of superconductor electronics fabrication technology. The developed testing technique allows for extracting margins of all individual cells in the shift register, which in turn makes it possible to estimate statistical distribution of Josephson junctions (JJs) in the circuit. We applied this approach to successfully test registers having 8-, 16-, 36-, and 202 thousand cells and, respectively, about 33-, 65-, 144-, and 809 thousand JJs. The circuits were fabricated at MIT Lincoln Laboratory, using a fully planarized process, 0.4-μm inductor linewidth and 1.33 × 106cm-2junction density. They are presently the largest operational superconducting SFQ circuits ever made. The developed technique distinguishes between “hard” defects (fabrication-related) and “soft” defects (measurement-related) and locates them in the circuit. The “soft” defects are specific to superconducting circuits and caused by magnetic flux trapping either inside the active cells or in the dedicated flux-trapping moats near the cells. The number and distribution of “soft” defects depend on the ambient magnetic field and vary with thermal cycling even if done in the same magnetic environment.