We diagnosed circuits to identify of margin reduction mechanisms in large-scale SFQ circuits. Two types of shift registers with partial or full bias line shields were designed and tested. We investigated the locations and origins of circuit errors by measuring bias margins and output waveforms. The results indicated that bias line currents can degrade the bias margin around the periphery in large-scale circuits with partial bias line shields. On the other hand, no apparent reduction of bias margins was observed in any part of the circuit area in the circuits with full bias line shields. However, we observed a reduction of the bias margin due to flux trapping even when we used a completely non-magnetic He dewar surrounded by a dual-layer permalloy metal shield. We found that the probability of finding a defect in a circuit with 10,000 Josephson junctions is less than 60%.
We diagnosed circuits to identify of margin reduction mechanisms in large-scale SFQ circuits. Two types of shift registers with partial or full bias line shields were designed and tested. We investigated the locations and origins of circuit errors by measuring bias margins and output waveforms. The results indicated that bias line currents can degrade the bias margin around the periphery in large-scale circuits with partial bias line shields. On the other hand, no apparent reduction of bias margins was observed in any part of the circuit area in the circuits with full bias line shields. However, we observed a reduction of the bias margin due to flux trapping even when we used a completely non-magnetic He dewar surrounded by a dual-layer permalloy metal shield. We found that the probability of finding a defect in a circuit with 10,000 Josephson junctions is less than 60%.
As the integration level of superconducting digital circuits increases, flux trapping in these devices becomes a serious problem. High resolution A/D converters and other high speed signal processing systems have been demonstrated with junction counts well into the 10/sup 3/ range. Such large circuits require special testing techniques to prevent flux trapping within the gates, which can reduce bias margins and cause malfunctions of these devices. We discuss the results of experiments using single flux quantum shift registers in which we have varied the ground plane hole pattern and magnetic shield degaussing procedure to minimize flux trapping in these circuits. The operating bias margins of the shift registers have been measured as a function of different testing procedures and ground plane hole designs. In situ degaussing of the magnetic shields aids in the reduction of flux trapping and gave the best results. Measurements of the permeability of mu metal at 4.2 K are discussed.
I Abstract -- As the integration level of superconducting digital circuits increases, flux trapping in these devices becomes a serious problem. High resolution A/D converters and other high speed signal processing systems have been demonstrated with junction counts well into the lo3 range. Such large circuits require special testing techniques to prevent flux trapping within the gates, which can reduce bias margins and cause malfunctions of these devices. We discuss the results of experiments using single flux quantum shift registers in which we have varied the ground plane hole pattern and magnetic shield degaussing procedure to minimize flux trapping in these circuits. The operating bias margins of the shift registers have been measured as a function of different testing procedures and ground plane hole designs. In situ degaussing of the magnetic shields aids in the reduction of flux trapping and gave the best results. Measurements of the permeability of mu metal at 4.2 K are discussed.
A variety of superconductor integrated circuits composed of six ac-powered SFQ shift registers with a total of 27078 bits and 108500 Josephson junctions (JJs) per 5 mm × 5 mm chip have been designed, fabricated, and tested to characterize flux trapping, fabrication process yield, and parameter spread. The six 4513-bit registers in the circuits have a common single-phase ac clock and individual input/output drivers, allowing for their parallel testing. We have investigated flux trapping in the circuits with various geometry, size, distance between moats in active ground planes (GPs), and containing up to three additional ‘dummy’ GPs, using multiple cooldowns through the critical temperature with various cooling rates and residual magnetic fields up to ∼ 1.2 µT. For the slit-type and square moats arrayed along the sides of the register cells, we have found a negligible effect of flux sequestered in the moats on the operating margins of the registers, and a negligible probability of detrimental flux trapping outside of the moats. Circuits with 0.3-µm-wide slit moats occupying less than 2% of the circuit area were fully operational in 100% of cooldowns, supporting the viability of a very large-scale integration of superconductor digital circuits. We have also found a strong enhancement of flux trapping outside the moats in circuits with closely spaced GPs and determined a critical distance,${{{\boldsymbol{t}}}_{\boldsymbol{c}}} \approx $0.6 µm, between them. The presence of two or more GPs spaced below thetcrendered the circuits nonoperational in 100% of cooldowns. We have measured 30 chips with over 3M JJs and determined individual cell operating margins in 138 registers to characterize the fabrication-related parameter spread and detect fabrication defects and flux-trapping events. By finding outlier bit-cells in the statistical distribution of the individual cell margins, we detected about one fabrication defect per million JJs, in most cases causing magnetic flux trapping in the affected cell.The circuits have been fabricated in the SFQ5ee fabrication process at MIT Lincoln Laboratory (MIT LL).
We develop an ac-biased shift register introduced in our previous work (V. K. Semenov et al., IEEE Trans. Appl. Supercond., vol. 25, no. 3, 1301507, June 2015) into a benchmark circuit for evaluation of superconductor electronics fabrication technology. The developed testing technique allows for extracting margins of all individual cells in the shift register, which in turn makes it possible to estimate statistical distribution of Josephson junctions (JJs) in the circuit. We applied this approach to successfully test registers having 8-, 16-, 36-, and 202 thousand cells and, respectively, about 33-, 65-, 144-, and 809 thousand JJs. The circuits were fabricated at MIT Lincoln Laboratory, using a fully planarized process, 0.4-μm inductor linewidth and 1.33 × 106cm-2junction density. They are presently the largest operational superconducting SFQ circuits ever made. The developed technique distinguishes between “hard” defects (fabrication-related) and “soft” defects (measurement-related) and locates them in the circuit. The “soft” defects are specific to superconducting circuits and caused by magnetic flux trapping either inside the active cells or in the dedicated flux-trapping moats near the cells. The number and distribution of “soft” defects depend on the ambient magnetic field and vary with thermal cycling even if done in the same magnetic environment.
The practical implementation of RSFQ technology in most digital electronics application areas requires much more complexity than the presently developed circuits. There are two important issues in building large-scale RSFQ circuits: 1) the recycling of the bias currents and 2) the transfer of SFQ pulses between circuits located far apart. RSFQ circuits are well known to operate with DC current bias. Even though the DC current biasing is more forgiving than the problematic AC biasing, it can still be a big concern when the circuit size becomes large. Dramatic reduction of the total bias current can be achieved by biasing several RSFQ circuits in series, where each circuit is positioned on a separate ground plane. In this work, we have used magnetically coupled Josephson transmission lines as inputs and outputs of an isolated shift register to show the feasibility of using the concept of serial biasing in current recycling. The circuit was simulated, fabricated with Nb technology, and tested at a temperature of 4.2 K. Test results show that SFQ pulses were transferred into the shift register built on a separate ground plane, clocked through it, and sent out back to the circuit on the original ground plane. We also studied on how to transfer SFQ pulses over an extended length, an important issue in building large RSFQ circuits. We have designed the circuits to test our microstrip line and multichip module approaches. We designed, optimized, fabricated and tested the circuits. Test results show that SFQ pulses can be successfully transmitted over an extensive distance in a chip and between chips.
The supply of bias current is one of the key problems to be overcome for fully operational large-scale SFQ circuits. Large currents cause various undesirable effects that degrade circuit operation. The magnetic field induced by a large DC bias current affects the operation of several SFQ cells, even with a microstrip-line structure applied for the bias lines. In this paper, experimental results using SQUIDs show that bias-line shielding is the most effective way to reduce the effect of the DC bias current. The operating margins of SFQ cells were also found to be sensitive to the current in the ground plane. The location of a ground bonding should be close to the point of current injection if we wish to avoid undesirable diffusion of current through the ground plane. We confirmed the effectiveness of bias-line shielding and of the location of ground bonding with a circuit composed of about 500 junctions.