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riven S~~f-Timed RSFQ Digital Integrate

Z.J. Deng, Nobuyuki Yoshikawa, Stephen R. Whiteley, T. Van Duzer

Published Jan 1, 1997• 0 citations
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Abstract

A~~t~a~~ --- A novel asynchronous timing scheme, ata-driven self-timing (DDST) is proposed and imple-Flux-Quantum (RSFQ) superircuits. In this asynchronous als are generated from the data ded to drive the RSFQ circuit the self-timing scheme is to g in order to avoid the overhead ion, and to minimize the timing scheme has been applied to the register, a demultiplexor, and a selfst system. In this paper, test register and a high speed onerator will be presented to demonstrate the ST operation of RSFQ integrated circuits at a rate of 20 Gbk.

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PIERS Online•Jan 1, 2005•1 citation
At~a --- A novel asynchronous timing scheme, ata-driven self-timing (DDST) is proposed and imple-Flux-Quantum (RSFQ) superircuits. In this asynchronous als are generated from the data ded to drive the RSFQ circuit the self-timing scheme is to g in order to avoid the overhead ion, and to minimize the timing scheme has been applied to the register, a demultiplexor, and a selfst system. In this paper, test register and a high speed onerator will be presented to demonstrate the ST operation of RSFQ integrated circuits at a rate of 20 Gbk.
A novel asynchronous timing scheme, data-driven self-timing (DDST) is proposed and implemented in Rapid Single-Flux-Quantum (RSFQ) superconductive integrated circuits. In this asynchronous approach, the timing signals are generated from the data and no global clock is needed to drive the RSFQ circuit and system. The essence of the self-timing scheme is to localize the system timing in order to avoid the overhead of global clock distribution, and to minimize the timing uncertainty. The DDST scheme has been applied to the design of a shift register, a demultiplexor, and a self-timed high speed digital test system. In this paper, test results of a 4-bit DDST shift register and a high speed on-chip clock generator will be presented to demonstrate the successful DDST operation of RSFQ integrated circuits at a rate of 20 Gb/s.
Superconductive Rapid Single Flux Quantum (RSFQ) logic and memory, in which ones and zeros are represented by the presence or absence within a timing window of quantized picosecond voltage pulse (/spl int/v(t)dt=h/2e=2.07 mV/spl middot/ps), corresponding to one SFQ, can be integrated into a digital computing system with an operating rate of several tens of GHz, based on the present Nb Josephson junction integrated circuit technology. It is the most promising technology beyond semiconductor transistors for low-power high-end computation. However, as the operating speed of circuits and systems increase, timing uncertainty from fabrication process variations makes global synchronization very hard. In this paper, we present a globally asynchronous, locally synchronous timing methodology for RSFQ digital design, which can solve the global synchronization problem. We also demonstrate the recent experimental results of some asynchronous circuits and systems implemented in RSFQ technology. Several key components such as a self-timed shift register, a self-timed demultiplexor, a Muller-C element, a completion detector, and a clock generator have been designed and tested. High speed operation has been confirmed up to 20 Gb/s for a prototype data buffer system, which consists two self-timed shift registers and an on-chip 5-38 GHz clock generator.
We have developed a data-driven self-timed (DDST) rapid-single-flux-quantum (RSFQ) demultiplexer (demux) for the interface between on-chip high-speed RSFQ circuits and off-chip low-speed circuits. In order to eliminate the timing issue in a synchronous clocking system we employed the DDST architecture, where a clock signal is localized within a 2-bit basic demux module and dual rail lines are used to transfer the timing information between the modules. A larger demux can be produced simply by connecting the 2-bit modules in a tree structure. The DDST demux was designed for 10 Gb/s operation with sufficient dc bias margin using HYPRES 1 kA/cm/sup 2/ Nb process. We have successfully tested operation of the 2-bit demux up to 18 GHz using the DDST on-chip high-speed test system which was developed in our group.
Rapid single flux quantum (RSFQ) logic is a digital circuit technology that in recent years has presented itself as an alternative to semiconductors in the application of ultra high speed, very low power applications. The optimal timing of digital circuits operating at hundreds of GHz is still a complex problem for both RSFQ and semiconductor technologies. The fact that most RSFQ gates require a clock signal to function makes this even more complex. Various RSFQ timing schemes have been adapted from semiconductor design methodologies, and some have been designed specifically for RSFQ. Currently, synchronous clocking schemes outperform other schemes, but with the scale of RSFQ circuits ever increasing, the proper use of timing schemes are becoming more crucial. This paper describes a new asynchronous self-timing scheme where the details of clock distribution and clocking are built into the logic gates. Tests were done on the newly developed asynchronous logic gates and an asynchronous full adder was implemented and tested
Rapid Single Flux Quantum (RSFQ) logic is a digital circuit technology that in recent years has presented itself as an alternative to semiconductors in the application of ultra high speed, very low power applications. The optimal timing of digital circuits operating at hundreds of Gigahertz is still a complex problem for both RSFQ and semiconductor technologies. The fact that most RSFQ gates require a clock signal to function makes this even more complex. Various RSFQ liming schemes have been adapted from semiconductor design methodologies, and some have been designed specifically for RSFQ. Currently, synchronous clocking schemes outperform other schemes, but with the scale of RSFQ circuits ever increasing, the proper use of timing schemes are becoming more crucial. This paper describes a new asynchronous self-timing scheme where the details of clock distribution and clocking are built into the logic gates. Tests were done on the newly developed asynchronous logic-gales and a asynchronous full adder was implemented and tested.
We present a novel asynchronous RSFQ digital circuit, Test-Timed RSFQ digital circuit and system(TT), in this paper. With this asynchronous approach, data is transferred in a delay-insensitive fashion to avoid the overhead of global clock distribution and the timing uncertainty. According to the scheme, the timing signal of the logic module is generated by a test logic module. The delay module can be removed from our circuit which should be used in previous asynchronous circuits. Finally, the simulation results for the Test-Timed data processing pipeline based on TT scheme are presented. 1.