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PIERS Online

Design and Simulation of RSFQ/RISC Computer System

Zhonghai Zhang, Boran Guan

Published Jan 1, 2005• 1 citation
Publisher

Abstract

We present a novel asynchronous RSFQ digital circuit, Test-Timed RSFQ digital circuit and system(TT), in this paper. With this asynchronous approach, data is transferred in a delay-insensitive fashion to avoid the overhead of global clock distribution and the timing uncertainty. According to the scheme, the timing signal of the logic module is generated by a test logic module. The delay module can be removed from our circuit which should be used in previous asynchronous circuits. Finally, the simulation results for the Test-Timed data processing pipeline based on TT scheme are presented. 1.

DOI
10.2529/piers041208100628

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We present a novel asynchronous RSFQ digital circuit, Test-Timed RSFQ digital circuit and system(TT), in this paper. With this asynchronous approach, data is transferred in a delay-insensitive fashion to avoid the overhead of global clock distribution and the timing uncertainty. According to the scheme, the timing signal of the logic module is generated by a test logic module. The delay module can be removed from our circuit which should be used in previous asynchronous circuits. Finally, the simulation results for the Test-Timed data processing pipeline based on TT scheme are presented. 1.
A novel asynchronous RSFQ digital circuit model, test-timed RSFQ digital model (TT) is proposed in this paper. With this asynchronous approach, data is transferred in a delay-insensitive fashion to avoid the problems aroused from the global clock distribution and the timing uncertainty. In the TT model, the timing pulse to the logic module will be generated with a test logic module, instead of the time delay module, which should be necessary in most asynchronous circuits. The elimination of the delay module can basically solve the timing uncertainty bothered in the RSFQ digital system layouts. The transient simulations and logic simulations have been made for the OR module and a RSFQ data processing pipeline based on the TT scheme has been designed. The logic simulations have also been made for this pipeline, and the results showed its feasibility and satisfaction for the RSFQ digital system applications.
A novel asynchronous timing scheme, data-driven self-timing (DDST) is proposed and implemented in Rapid Single-Flux-Quantum (RSFQ) superconductive integrated circuits. In this asynchronous approach, the timing signals are generated from the data and no global clock is needed to drive the RSFQ circuit and system. The essence of the self-timing scheme is to localize the system timing in order to avoid the overhead of global clock distribution, and to minimize the timing uncertainty. The DDST scheme has been applied to the design of a shift register, a demultiplexor, and a self-timed high speed digital test system. In this paper, test results of a 4-bit DDST shift register and a high speed on-chip clock generator will be presented to demonstrate the successful DDST operation of RSFQ integrated circuits at a rate of 20 Gb/s.
Superconductive Rapid Single Flux Quantum (RSFQ) logic and memory, in which ones and zeros are represented by the presence or absence within a timing window of quantized picosecond voltage pulse (/spl int/v(t)dt=h/2e=2.07 mV/spl middot/ps), corresponding to one SFQ, can be integrated into a digital computing system with an operating rate of several tens of GHz, based on the present Nb Josephson junction integrated circuit technology. It is the most promising technology beyond semiconductor transistors for low-power high-end computation. However, as the operating speed of circuits and systems increase, timing uncertainty from fabrication process variations makes global synchronization very hard. In this paper, we present a globally asynchronous, locally synchronous timing methodology for RSFQ digital design, which can solve the global synchronization problem. We also demonstrate the recent experimental results of some asynchronous circuits and systems implemented in RSFQ technology. Several key components such as a self-timed shift register, a self-timed demultiplexor, a Muller-C element, a completion detector, and a clock generator have been designed and tested. High speed operation has been confirmed up to 20 Gb/s for a prototype data buffer system, which consists two self-timed shift registers and an on-chip 5-38 GHz clock generator.
A~~t~a~~ --- A novel asynchronous timing scheme, ata-driven self-timing (DDST) is proposed and imple-Flux-Quantum (RSFQ) superircuits. In this asynchronous als are generated from the data ded to drive the RSFQ circuit the self-timing scheme is to g in order to avoid the overhead ion, and to minimize the timing scheme has been applied to the register, a demultiplexor, and a selfst system. In this paper, test register and a high speed onerator will be presented to demonstrate the ST operation of RSFQ integrated circuits at a rate of 20 Gbk.
A microprocessor test vehicle was developed for the investigation of asynchronous design methodology for rapid- single-flux-quantum (RSFQ) circuits. We have designed and implemented a fully asynchronous RSFQ microprocessor, named SCRAM2. The data-driven self-timing (DDST) architecture is used for the design of circuit blocks of the SCRAM2. In order to ensure the logical ordering between the circuit blocks, bit-serial handshaking was adopted. The performance of the handshaking system was enhanced based on the scalable-delay-insensitive (SDI) model. The SCRAM2 is an 8-bit bit-serial microprocessor with three-stage pipelining, with a basic microarchitecture similar to that of our previously designed synchronous microprocessor, CORE1alpha. The estimated average performance of the SCRAM2 is 577 MIPS using a logic simulation. We have implemented all circuit components using the SRL 2.5 kA/cm2Nb process and confirmed their correct operation. Several operations of the SCRAM2 have been successfully confirmed.
Rapid single flux quantum (RSFQ) logic is a digital circuit technology that in recent years has presented itself as an alternative to semiconductors in the application of ultra high speed, very low power applications. The optimal timing of digital circuits operating at hundreds of GHz is still a complex problem for both RSFQ and semiconductor technologies. The fact that most RSFQ gates require a clock signal to function makes this even more complex. Various RSFQ timing schemes have been adapted from semiconductor design methodologies, and some have been designed specifically for RSFQ. Currently, synchronous clocking schemes outperform other schemes, but with the scale of RSFQ circuits ever increasing, the proper use of timing schemes are becoming more crucial. This paper describes a new asynchronous self-timing scheme where the details of clock distribution and clocking are built into the logic gates. Tests were done on the newly developed asynchronous logic gates and an asynchronous full adder was implemented and tested