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Effect ofCheck Node Processingon thePerformance of Message PassingAlgorithmintheContext of LDPC Decoding forDVB-S2

M Girish Chandra, S.G. Harihara, B. S. Adiga, P. Balamuralidhar, Prerna Subramanian

Published Jan 1, 2005• 0 citations
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Abstract

LowDensity Parity Check(LDPC)codes havebecome verypopular inrecent times duetotheir capacity approaching performance andareconsidered inthenextgeneration digital videobroadcasting DVB-S2standard. Thispaperpresents few results andobservations obtained whensomeoftheexisting decoding algorithms are studied in thecontextof the standardized codes. Theseresults withfurther consolidation will facilitate toarrive attheright algorithm fordecoder design.

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Effect of Check Node Processing on the Performance of Message Passing Algorithm in the Context of LDPC Decoding for DVB-S2

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Low density parity check (LDPC) codes have become very popular in recent times due to their capacity approaching performance and are considered in the next generation digital video broadcasting DVB-S2 standard. This paper presents few results and observations obtained when some of the existing decoding algorithms are studied in the context of the standardized codes. These results with further consolidation will facilitate to arrive at the right algorithm for decoder design

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•Jan 1, 2005•0 citations
LowDensity Parity Check(LDPC)codes havebecome verypopular inrecent times duetotheir capacity approaching performance andareconsidered inthenextgeneration digital videobroadcasting DVB-S2standard. Thispaperpresents few results andobservations obtained whensomeoftheexisting decoding algorithms are studied in thecontextof the standardized codes. Theseresults withfurther consolidation will facilitate toarrive attheright algorithm fordecoder design.
LowDensity Parity Check(LDPC)decoders imple- menting longblocklength codesrequire semi-parallel design. One challenge whenimplementing these codes onField Programmable GateArrays(FPGAs)isefficiently storing messages neededin theiteration process. Tomeetthis challenge, anewclass ofLDPC codesispresented. Theycombineregularity ofimplementation withreduction oftimeneededfordecoding process, anddonot suffer ofanysignificant performance loss duetotheir structure. I.INTRODUCTION Lowdensity parity check(LDPC)codes havegarnered a great deal ofattention intheerror control coding field recently, duetotheability toimplement soft-decision decoders that perform veryneartheShannon bound(for longblocklengths). Thedecoding algorithm isiterative, using message passing amongnodes inaTanner graph representation ofthecode, and allows parallel, orsemi-parallel processing inthecomputation tospeed decoding.
The Low-Density Parity-Check codes are among the most powerful forward error correcting codes, since they enable to get as close as a fraction of a dB from the Shannon limit.This astonishing performance combined with their relatively simple decoding algorithmmake these codes very attractive for the next digital transmission system generations. Itis already the case for the next digital satellite broadcasting standard (DVB-S2), where an irregular LDPC code has been chosen to protect the downlink information. In this thesis, we focused our research on the iterative decoding algorithms and their hardware implementations. We proposed first a suboptimal algorithm named the λ-min algorithm. It reduces significantly the complexity of the decoder without any significant performance loss, as compared to the belief propagation (BP) algorithm. Then we studied and designed a generic architecture of an LDPC decoder, which has been implemented on a FPGA based platform. This hardware decoder enables to accelerate the simulations more than 500 times as compared to software simulations. Moreover, based on an all-tunable design, our decoder features many facilities: It is possible to configure it for a very wide code family, so that the research for good codes is processed faster ; thanks to the genericity of the processing components, it is also possible to optimize the internal coding format, and even to compare various decoding algorithms and various processing schedules. Finally, our experience in the area of LDPC decoders led us to propose a formal framework for analysing the architectures of LDPC decoders. This framework encompassesboth the datapath (parallelism, node processors architectures) and the control mode associated to the several decoding schedules. Thus within this framework, a classification of the different state-of-the-art LDPC decoders is proposed. Moreover, some synthesis of efficient and unpublished architectures have been also proposed.
The Low-Density Parity-Check codes are among the most powerful forward error correcting codes, since they enable to get as close as a fraction of a dB from the Shannon limit.This astonishing performance combined with their relatively simple decoding algorithmmake these codes very attractive for the next digital transmission system generations. Itis already the case for the next digital satellite broadcasting standard (DVB-S2), where an irregular LDPC code has been chosen to protect the downlink information. In this thesis, we focused our research on the iterative decoding algorithms and their hardware implementations. We proposed first a suboptimal algorithm named the λ-min algorithm. It reduces significantly the complexity of the decoder without any significant performance loss, as compared to the belief propagation (BP) algorithm. Then we studied and designed a generic architecture of an LDPC decoder, which has been implemented on a FPGA based platform. This hardware decoder enables to accelerate the simulations more than 500 times as compared to software simulations. Moreover, based on an all-tunable design, our decoder features many facilities: It is possible to configure it for a very wide code family, so that the research for good codes is processed faster ; thanks to the genericity of the processing components, it is also possible to optimize the internal coding format, and even to compare various decoding algorithms and various processing schedules. Finally, our experience in the area of LDPC decoders led us to propose a formal framework for analysing the architectures of LDPC decoders. This framework encompasses both the datapath (parallelism, node processors architectures) and the control mode associated to the several decoding schedules. Thus within this framework, a classification of the different state-of-the-art LDPC decoders is proposed. Moreover, some synthesis of efficient and unpublished architectures have been also proposed.
Low-density parity-check codes (LDPC) are among the most powerful error correcting tools today available. For this reason they became very popular in several applications such as the digital satellite broadcasting system (DVB-S2), wireless local area network (IEEE 802.11n) and metropolitan area network (802.16e). Whereas several code-specific decoders have been proposed in the literature, the implementation of a high performance yet flexible LDPC decoder still is a challenging topic. This work presents a novel formulation of the decoding algorithm that strongly simplifies internal communication requirements and enables the development of decoders supporting generally defined LDPC codes. The resulting architecture is tailored to decode both IEEE 802.11n and IEEE 802.16e LDPC codes, as well as any other code of comparable complexity. The implementation cost deriving from the full flexibility offered by the proposed approach is also evaluated.
The class of low-density parity-check (LDPC) codes was introduced by Gallager in his thesis in 1961 [2]. Until the invention of turbo codes, they were largely neglected, but received a lot of interest lately, due to the possibility of designing LDPC codes within 0:0045 dB of the Shannon limit. We review in this project techniques used to analyze the performance of LDPC codes under a message-passing decoding algorithm, namely belief propagation (BP) [4][5]. This analysis gives us the tools to design good LDPC codes. We will flrst take the simpler example of transmission over the class of binary erasure channels (BEC). We will then see how it is possible to extend the results for the BEC to the much more general class of symmetric channels.