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International Conference on Information, Communications & Signal Processing (ICICS)

Effect of Check Node Processing on the Performance of Message Passing Algorithm in the Context of LDPC Decoding for DVB-S2

M Girish Chandra, S.G. Harihara, B. S. Adiga, P. Balamuralidhar, P.S. Subramanian

Published Sep 22, 2006• 7 citations
Publisher

Abstract

Low density parity check (LDPC) codes have become very popular in recent times due to their capacity approaching performance and are considered in the next generation digital video broadcasting DVB-S2 standard. This paper presents few results and observations obtained when some of the existing decoding algorithms are studied in the context of the standardized codes. These results with further consolidation will facilitate to arrive at the right algorithm for decoder design

DOI
10.1109/icics.2005.1689281

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Low density parity check (LDPC) codes have become very popular in recent times due to their capacity approaching performance and are considered in the next generation digital video broadcasting DVB-S2 standard. This paper presents few results and observations obtained when some of the existing decoding algorithms are studied in the context of the standardized codes. These results with further consolidation will facilitate to arrive at the right algorithm for decoder design
Low density parity check code being the most powerful Error correcting code with performance near to Shannon limit is studied and simulated in this paper. Because of its performance it is used in Digital Video Broadcasting Satellite for Second Generation (DVBS2).In this paper, LDPC encoding algorithm named “Irregular repeat accumulated code” has been illustrated in detail. There are several algorithms existing for the decoding of the LDPC decoder. Among them here, two decoding algorithm named “Turbo decoding message passing Algorithm” and “Two phase message passing algorithm” has been illustrated and simulated in MATLAB. The results comparing these two decoding algorithms and different iterations have been presented in this paper.
Abstract: In this paper, a fast-convergence algorithm is proposed for the decoding of low-density parity-check (LDPC) codes. By putting more weight on the message update from check node to variable node in current iteration, the proposed method speeds up the decoding significantly. Simulation results show that compared with the standard layered min-sum decoding algorithm, the proposed scheme may reduce about 1/6 iteration numbers for LDPC codes used in DVB-S2, with hardware complexity overhead less than 2%. Key–Words: LDPC code, fast convergence decoding algorithm, layered decoding, min-sum algorithm, hardware implementation 1
In this paper, a new approximation of the check node rule algorithm is proposed for updating the check nodes messages in LDPC decoding. The new technique evaluates the check node min-sum magnitude algorithm using the Taylor series and results in reduced computational complexity and hardware implementation. The architecture of a check node processing unit, implementing the new alternative approximation of the check node, is also presented. The proposed method can achieve the same BER performance with a reduction of ~20% hardware complexity in the LDPE decoder. The simulation results obtained shows that the packet error rate performance of 10-7, which is the DVB-S2 requirement for MPEG packets transmitted, can be achieved with this new method.
Low-density parity-check codes (LDPC) are among the most powerful error correcting tools today available. For this reason they became very popular in several applications such as the digital satellite broadcasting system (DVB-S2), wireless local area network (IEEE 802.11n) and metropolitan area network (802.16e). Whereas several code-specific decoders have been proposed in the literature, the implementation of a high performance yet flexible LDPC decoder still is a challenging topic. This work presents a novel formulation of the decoding algorithm that strongly simplifies internal communication requirements and enables the development of decoders supporting generally defined LDPC codes. The resulting architecture is tailored to decode both IEEE 802.11n and IEEE 802.16e LDPC codes, as well as any other code of comparable complexity. The implementation cost deriving from the full flexibility offered by the proposed approach is also evaluated.
The Low-Density Parity-Check codes are among the most powerful forward error correcting codes, since they enable to get as close as a fraction of a dB from the Shannon limit.This astonishing performance combined with their relatively simple decoding algorithmmake these codes very attractive for the next digital transmission system generations. Itis already the case for the next digital satellite broadcasting standard (DVB-S2), where an irregular LDPC code has been chosen to protect the downlink information. In this thesis, we focused our research on the iterative decoding algorithms and their hardware implementations. We proposed first a suboptimal algorithm named the λ-min algorithm. It reduces significantly the complexity of the decoder without any significant performance loss, as compared to the belief propagation (BP) algorithm. Then we studied and designed a generic architecture of an LDPC decoder, which has been implemented on a FPGA based platform. This hardware decoder enables to accelerate the simulations more than 500 times as compared to software simulations. Moreover, based on an all-tunable design, our decoder features many facilities: It is possible to configure it for a very wide code family, so that the research for good codes is processed faster ; thanks to the genericity of the processing components, it is also possible to optimize the internal coding format, and even to compare various decoding algorithms and various processing schedules. Finally, our experience in the area of LDPC decoders led us to propose a formal framework for analysing the architectures of LDPC decoders. This framework encompassesboth the datapath (parallelism, node processors architectures) and the control mode associated to the several decoding schedules. Thus within this framework, a classification of the different state-of-the-art LDPC decoders is proposed. Moreover, some synthesis of efficient and unpublished architectures have been also proposed.