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International Conference on Systems and Networks Communications

Alternative Approximation of Check Node Algorithm for DVB-S2 LDPC Decoder

O. Eljamaly Toumaz, P. Sweeney

Published Aug 1, 2007• 5 citations
Publisher

Abstract

In this paper, a new approximation of the check node rule algorithm is proposed for updating the check nodes messages in LDPC decoding. The new technique evaluates the check node min-sum magnitude algorithm using the Taylor series and results in reduced computational complexity and hardware implementation. The architecture of a check node processing unit, implementing the new alternative approximation of the check node, is also presented. The proposed method can achieve the same BER performance with a reduction of ~20% hardware complexity in the LDPE decoder. The simulation results obtained shows that the packet error rate performance of 10-7, which is the DVB-S2 requirement for MPEG packets transmitted, can be achieved with this new method.

DOI
10.1109/icsnc.2007.13

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In this paper, a new approximation of the check node rule algorithm is proposed for updating the check nodes messages in LDPC decoding. The new technique evaluates the check node min-sum magnitude algorithm using the Taylor series and results in reduced computational complexity and hardware implementation. The architecture of a check node processing unit, implementing the new alternative approximation of the check node, is also presented. The proposed method can achieve the same BER performance with a reduction of ~20% hardware complexity in the LDPE decoder. The simulation results obtained shows that the packet error rate performance of 10-7, which is the DVB-S2 requirement for MPEG packets transmitted, can be achieved with this new method.
One of the most important units of Low-Density Parity-Check (LDPC) decoders is the Check-Node Unit.Its main task is to find the first two minimum values among incoming variable-to-check messages and return check-tovariable messages.This block significantly affects the decoding performance, as well as the hardware implementation complexity.In this paper, we first propose a modification to the check-node update rule by introducing two optimal offset factors applied to the check-to-variable messages.Then, we present the Check-Node Unit hardware architecture which performs the proposed algorithm.The main objective of this work aims to improve further the decoding performance for 5 th Generation (5G) LDPC codes.The simulation results show that the proposed algorithm achieves essential improvements in terms of error correction performance.More precisely, the error-floor does not appear within Bit-Error-Rate (BER) of 10 -8 , while the decoding gain increases up to 0.21 dB compared to the baseline Normalized Min-Sum, as well as several state-ofthe-art LDPC-based Min-Sum decoders.
Abstract: In this paper, a fast-convergence algorithm is proposed for the decoding of low-density parity-check (LDPC) codes. By putting more weight on the message update from check node to variable node in current iteration, the proposed method speeds up the decoding significantly. Simulation results show that compared with the standard layered min-sum decoding algorithm, the proposed scheme may reduce about 1/6 iteration numbers for LDPC codes used in DVB-S2, with hardware complexity overhead less than 2%. Key–Words: LDPC code, fast convergence decoding algorithm, layered decoding, min-sum algorithm, hardware implementation 1
An improved decoding algorithm for low-density parity-check (LDPC) codes is presented. By taking advantages of the first-term Taylor’s series multiple expansion to approximate the correction term of the Jacobian logarithm used in LLR-SPA (log-likelihood ratio sum-product algorithm), we propose an algorithm which significantly simplifies the check node update computation of the optimal LLR-SPA. Besides, the parameter δ is introduced to determine suitable expansion points. The simulation result shows that the proposed method with ten expansion points when δ is set to 0.01 has almost identical performance compared with ideal SPA algorithm and outperforms both the min-sum algorithm (MS), the offset min-sum algorithm (OMS) and the normalised min-sum algorithm (NMS). The architecture of proposed method is also presented for implementation, which has reduced computational complexity and is feasible for hardware implementation.
This paper has presented various min-sum related LDPC decoding algorithms and their typical hardware architectures of check node update in the scenario of parallel implementation. The m-to-2m decoder has been introduced to generate more efficient new hardware implementations of check node update, which can obviously reduce the number of multiplication operations for normalized min-sum algorithm for high rate LDPC codes. Simulations have claimed the performance of normalized min-sum is nearly the same as that of Log-BP, namely the optimal algorithm. In general, this paper has proved that normalized min-sum is good choices as LDPC decoding methods.
In this paper, a novel self-adjustable offset min-sum LDPC decoding algorithm is proposed for ISDB-S2 (Integrated Services Digital Broadcasting via Satellite — Second Generation) application. We present for the first time a uniform approximation of the check node operation through mathematical induction on Jacobian logarithm. The approximation theoretically shows that the offset value is mainly dependent on the difference between the two most unreliable inputs from the bit nodes and the algorithm proposed can adjust the offset value according to the inputs during the iterative decoding procedure. Simulation results for all 11 code rates of ISDB-S2 demonstrate that the proposed method can achieve an average of 0.15dB gain under the same Bit Error Rate (BER) performance, compared to the Min-sum based algorithms, and consumes only 1.21% computation complexity compared to BP-based algorithms in the best case.