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IEEE Transactions on Applied Superconductivity

Simulation Study of High- $T_rm c$ Superconducting Sampler Circuit With Bandwidth Over 100 GHz

Michitaka Maruyama, Hideo Suzuki, Tsunehiro Hato, K. Tanabe

Published Jun 1, 2005• 8 citations
Publisher

Abstract

We investigated high-T/sub c/ superconducting sampler circuits by computer simulation and proved that our latest version of sampler circuit can operate with bandwidth over 100 GHz. In our conventional sampler circuit, we found several problems in its circuit design. An improved sampler circuit, which has additional reset junctions in the dc/SFQ and SFQ/dc parts of the circuit and has a Josephson transmission line with an optimized dc bias in front of the comparator, accurately reconstructed signal waveforms with bandwidth above 160 GHz for a typical I/sub c/R/sub n/ product of 1 mV in the simulation.

DOI
10.1109/tasc.2005.849816

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Simulation Study of High- TrmcT_rm cTr​mc Superconducting Sampler Circuit With Bandwidth Over 100 GHz
We investigated high-T/sub c/ superconducting sampler circuits by computer simulation and proved that our latest version of sampler circuit can operate with bandwidth over 100 GHz. In our conventional sampler circuit, we found several problems in its circuit design. An improved sampler circuit, which has additional reset junctions in the dc/SFQ and SFQ/dc parts of the circuit and has a Josephson transmission line with an optimized dc bias in front of the comparator, accurately reconstructed signal waveforms with bandwidth above 160 GHz for a typical I/sub c/R/sub n/ product of 1 mV in the simulation.
This paper reviews our progress on the high-T c superconducting (HTS) sampler development, covering from the circuit design to the latest experimental data in the sinusoidal and pulse waveform measurements. A computer simulation has revealed that our sampler circuit with an improved design enables waveform measurement with the bandwidth over 100 GHz even with the thermal noise at around 40 K. Using the HTS sampler circuits fabricated employing an improved layout, we demonstrated waveform measurements for sinusoidal signals with frequencies of up to 50 GHz, the upper limit of the signal generator we used, both in the voltage-input-type system with a high-frequency input line and in the current-input-type one with a superconducting pickup coil. In the pulse measurement using an on-chip sampler, we succeeded in observing pico-second-order-wide single flux quantum (SFQ) current pulses, suggesting the potential bandwidth of our HTS sampler of more than 125 GHz.
Measurement of signals generated by superconducting Josephson junction (JJ) circuits require ultra-fast components located in close proximity to the generating circuitry. We report a detailed study of optimal design criteria for a JJ-based sampler which balances the highest sampler bandwidth (shortest 10\%--90\% rise time) with minimal sampled waveform distortion. We explore the impacts on performance of a sampler, realized using a single underdamped JJ as the logical sampling element (the comparator), due to the type of signal-comparator coupling scheme that is utilized (galvanic, inductive, or capacitive). In these simulations we emulate the entire waveform reconstruction sampling process, via comparator threshold detection, while sweeping the time location at which the waveform is being sampled. We extract the sampled waveform rise time (or FWHM) as a function of the comparator's Stewart-McCumber parameter and as a function of the coupling strength between the device under test and comparator. Based on our simulation results we design, fabricate, and characterize a cryocooled (3.6 K operating temperature) JJ sampler utilizing the NIST state-of-the-art Nb/amorphous-Si/Nb junctions. We separately sample a step signal and impulse generator co-located on-chip with the comparator and sampling strobe generator by implementing the same binary search comparator threshold detection technique during sampler operation as is used in simulation. With this technique the system is fully-digital and automated and operation of the fabricated device directly mirrors simulation. Our sampler technology shows a 10\%--90\% rise time of 3.3 ps and the capability to measure transient pulse widths of 2.5 ps FWHM. A linear systems analysis of sampled waveforms indicate a 3 dB bandwidth of 225 GHz, but we demonstrate effective measurement of signals well above this -- as high as 600 GHz.
Measurement of signals generated by superconducting Josephson junction (JJ) circuits require ultra-fast components located in close proximity to the generating circuitry. We report a detailed study of optimal design criteria for a JJ-based sampler that balances the highest sampler bandwidth (shortest 10%-90% rise time) with minimal sampled waveform distortion. We explore the impacts on the performance of a sampler, realized using a single underdamped JJ as the logical sampling element (the comparator), due to the type of signal-comparator coupling scheme that is utilized (galvanic, inductive, or capacitive). In these simulations, we emulate the entire waveform reconstruction sampling process, via comparator threshold detection, while sweeping the time location at which the waveform is being sampled. We extract the sampled waveform rise time [or full width at half maximum (FWHM)] as a function of the comparator's Stewart-McCumber parameter and as a function of the coupling strength between the device under test and comparator. Based on our simulation results, we design, fabricate, and characterize a cryocooled (3.6 K operating temperature) JJ sampler utilizing the NIST state-of-the-art Nb/amorphous-Si/Nb junctions. We separately sample a step signal and an impulse generator co-located on-chip with the comparator and sampling strobe generator by implementing the same binary search comparator threshold detection technique during sampler operation as is used in simulation. With this technique, the system is fully digital and automated, and the operation of the fabricated device directly mirrors simulation. Our sampler technology shows a 10%-90% rise time of 3.3 ps and the capability to measure transient pulse widths of 2.5 ps FWHM. A linear system analysis of sampled waveforms indicates a 3 dB bandwidth of 225 GHz, but we demonstrate effective measurement of signals well above this-as high as 600 GHz.
We fabricated and tested high-temperature superconducting (HTS) rapid-single-flux-quantum (RSFQ) circuits using interface-engineered Josephson junction (IEJ). The characteristics of high-speed operation were examined by voltage-divider operation based on the toggle-flip-flop circuit. An operation at 155 GHz was obtained at 15 K and the proper functioning of the voltage divider was observed up to 27 K. Temperature dependence of the maximum operation speed was analyzed by circuit simulation with thermal-noise sources. To achieve higher speed operation using a Josephson junction with a higher I/sub c/R/sub n/ product, we also fabricated an RSFQ balanced comparator using IEJ; proper switching characteristics of the circuit was confirmed up to 190 GHz at 30 K. The bias condition dependencies were studied based on the circuit simulations in the relationship of the I/sub c/R/sub n/ product. The results of circuit simulation indicate that a Josephson junction with an I/sub c/R/sub n/ product of more than 0.7 mV is required for high-speed operation (100 GHz) in high-temperature range (30-40 K). We believe that the IEJ is a promising junction candidate for realizing high-speed operation in a high-temperature range.
We are developing a system using a high-T/sub c/ superconductor (HTS) sampler for measuring a 40-Gbps digital signal waveform, which will be used in next generation ultra-high-speed communications. To measure a 40-Gbps digital signal, the sampler bandwidth needs to be more than 120 GHz. The HTS sampler has the potential to achieve this bandwidth. As a first step in developing this system, we have developed a prototype whose target bandwidth is 40 GHz. In the prototype system, the sampler chip is cooled down to 35 K by a single-stage Stirling cryocooler, and the digital signal is transmitted to the sampler chip via a 40-GHz bandwidth assembly line. This system is the first to integrate an HTS device, a cryocooler, and a high-frequency assemble line. A 5.9-Gbps digital waveform was reconstituted by the prototype system with the correct period.