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IEEE Transactions on Applied Superconductivity

High-T/sub c/ superconductor sampler system for digital signal waveform measurement

Mutsuo Hidaka, T. Satoh, Masato Kimishima, M. Takayama, Shuichi Tahara

Published Mar 1, 2001• 20 citations
Publisher

Abstract

We are developing a system using a high-T/sub c/ superconductor (HTS) sampler for measuring a 40-Gbps digital signal waveform, which will be used in next generation ultra-high-speed communications. To measure a 40-Gbps digital signal, the sampler bandwidth needs to be more than 120 GHz. The HTS sampler has the potential to achieve this bandwidth. As a first step in developing this system, we have developed a prototype whose target bandwidth is 40 GHz. In the prototype system, the sampler chip is cooled down to 35 K by a single-stage Stirling cryocooler, and the digital signal is transmitted to the sampler chip via a 40-GHz bandwidth assembly line. This system is the first to integrate an HTS device, a cryocooler, and a high-frequency assemble line. A 5.9-Gbps digital waveform was reconstituted by the prototype system with the correct period.

DOI
10.1109/77.919335

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Measurement of signals generated by superconducting Josephson junction (JJ) circuits require ultra-fast components located in close proximity to the generating circuitry. We report a detailed study of optimal design criteria for a JJ-based sampler that balances the highest sampler bandwidth (shortest 10%-90% rise time) with minimal sampled waveform distortion. We explore the impacts on the performance of a sampler, realized using a single underdamped JJ as the logical sampling element (the comparator), due to the type of signal-comparator coupling scheme that is utilized (galvanic, inductive, or capacitive). In these simulations, we emulate the entire waveform reconstruction sampling process, via comparator threshold detection, while sweeping the time location at which the waveform is being sampled. We extract the sampled waveform rise time [or full width at half maximum (FWHM)] as a function of the comparator's Stewart-McCumber parameter and as a function of the coupling strength between the device under test and comparator. Based on our simulation results, we design, fabricate, and characterize a cryocooled (3.6 K operating temperature) JJ sampler utilizing the NIST state-of-the-art Nb/amorphous-Si/Nb junctions. We separately sample a step signal and an impulse generator co-located on-chip with the comparator and sampling strobe generator by implementing the same binary search comparator threshold detection technique during sampler operation as is used in simulation. With this technique, the system is fully digital and automated, and the operation of the fabricated device directly mirrors simulation. Our sampler technology shows a 10%-90% rise time of 3.3 ps and the capability to measure transient pulse widths of 2.5 ps FWHM. A linear system analysis of sampled waveforms indicates a 3 dB bandwidth of 225 GHz, but we demonstrate effective measurement of signals well above this-as high as 600 GHz.
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We investigated high-T/sub c/ superconducting sampler circuits by computer simulation and proved that our latest version of sampler circuit can operate with bandwidth over 100 GHz. In our conventional sampler circuit, we found several problems in its circuit design. An improved sampler circuit, which has additional reset junctions in the dc/SFQ and SFQ/dc parts of the circuit and has a Josephson transmission line with an optimized dc bias in front of the comparator, accurately reconstructed signal waveforms with bandwidth above 160 GHz for a typical I/sub c/R/sub n/ product of 1 mV in the simulation.
Superconducting devices have intrinsically superior characteristics to those of semiconductor devices. Presently, we can fabricate more than twenty thousand junctions on one chip using niobium technology. We have demonstrated the operation of a network system with a superconducting interconnection chip using voltage-state logic. Single flux quantum devices are promising for future superconducting applications because the clock frequency of SFQ logic is higher than that of voltage-state. We have proposed a high-end switch based on hybrid architecture using optical devices, semiconductors and SFQ devices. To demonstrate the high-speed operation of SFQ circuits, we developed an arbiter circuit that uses SFQ components and the arbiter circuit operates at 60 GHz. We also have developed a high Tc superconducting (HTS) SFQ sampler system for observing ultra-fast signal waveforms. In addition, we will discuss the prospects of future superconducting devices based on the fabrication technologies we developed.