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IEEE Transactions on Applied Superconductivity

Circuit design for a high-T/sub c/ Josephson sampler

Mutsuo Hidaka, J. S. Tsai

Published Jun 1, 1995• 18 citations
Publisher

Abstract

We propose a high-speed and high-sensitivity sampler circuit using high T/sub c/ superconducting (HTS) Josephson junctions. This circuit consists of five non-latching junctions, superconducting lines and a superconducting ground-plane. A main feature of this circuit is a non-latching comparator junction whose switching generates a circulating current in a superconducting loop. Computer simulation and prototype layout were performed to study its ability and feasibility.>

DOI
10.1109/77.403310

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Simulation Study of High- TrmcT_rm cTr​mc Superconducting Sampler Circuit With Bandwidth Over 100 GHz
We investigated high-T/sub c/ superconducting sampler circuits by computer simulation and proved that our latest version of sampler circuit can operate with bandwidth over 100 GHz. In our conventional sampler circuit, we found several problems in its circuit design. An improved sampler circuit, which has additional reset junctions in the dc/SFQ and SFQ/dc parts of the circuit and has a Josephson transmission line with an optimized dc bias in front of the comparator, accurately reconstructed signal waveforms with bandwidth above 160 GHz for a typical I/sub c/R/sub n/ product of 1 mV in the simulation.
The design and experimental investigation of a simple logic circuit employing Josephson tunnel junctions as the switching elements is described. The design utilized matched transmission lines as signal carriers. The physical layout was simulated on a computer with a model consisting of 3 Josephson gates and 28 transmission line segments. Results of both quasi-static and high speed testing were found to be in essential agreement with theoretical expectations; only dynamic results are presented here in detail. The experimental circuit had gates with 165 ps risetimes, and in the high speed investigation, was operated with bursts of 700 ps risetime pulses tightly spaced so as to simulate a repetition rate of ∼1 GHz.
We fabricated and tested high-temperature superconducting (HTS) rapid-single-flux-quantum (RSFQ) circuits using interface-engineered Josephson junction (IEJ). The characteristics of high-speed operation were examined by voltage-divider operation based on the toggle-flip-flop circuit. An operation at 155 GHz was obtained at 15 K and the proper functioning of the voltage divider was observed up to 27 K. Temperature dependence of the maximum operation speed was analyzed by circuit simulation with thermal-noise sources. To achieve higher speed operation using a Josephson junction with a higher I/sub c/R/sub n/ product, we also fabricated an RSFQ balanced comparator using IEJ; proper switching characteristics of the circuit was confirmed up to 190 GHz at 30 K. The bias condition dependencies were studied based on the circuit simulations in the relationship of the I/sub c/R/sub n/ product. The results of circuit simulation indicate that a Josephson junction with an I/sub c/R/sub n/ product of more than 0.7 mV is required for high-speed operation (100 GHz) in high-temperature range (30-40 K). We believe that the IEJ is a promising junction candidate for realizing high-speed operation in a high-temperature range.
A new current-injection Josephson latch employing a single-flux quantum is proposed. It has a master-slave circuit configuration and operates under ac power supply. In the circuit, data are stored as a circulating current in a superconducting loop consisting of a single junction and inductances. A two-junction interferometer gate directly coupled to the loop reads out the stored data. Dual-rail signals are generated from the read-out data by Josephson junctions and resister-coupled Josephson logic gates. The isolation between a master circuit and a slave circuit is realized using high-impedance states in the Josephson junctions. The circuit design and computer-simulation results on the circuit operation are described in this paper.