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IEEE Transactions on Applied Superconductivity

Short-term frequency stability of RSFQ ring oscillators

C.A. Mancini, Mark F. Bocko

Published Jun 1, 1999• 9 citations
Publisher

Abstract

The temporal stability of the clock signal has a profound effect on the performance of synchronous RSFQ digital systems. Short-term clock fluctuations, or clock jitter, can severely degrade system performance due to the hazard of timing constraint violations. Successful large-scale RSFQ digital systems will require highly stable multi-Gigahertz on-chip clock sources. To meet this need, methods for characterizing and measuring the short-term stability of such sources are required. In this paper we identify the relevant figure of merit to characterize and compare various clocks: the cycle-to-cycle standard deviation of the clock periods. We have developed experimental techniques for the measurement of this figure of merit and applied it to the characterization of an RSFQ ring oscillator. The experimental results are compared with results from a stochastic circuit simulator. We determined the value of jitter to be 1.52% at 10 GHz.

DOI
10.1109/77.783795

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The temporal stability of the clock signal has a profound effect on the performance of synchronous RSFQ digital systems. Short-term clock fluctuations, or clock jitter, can severely degrade system performance due to the hazard of timing constraint violations. Successful large-scale RSFQ digital systems will require highly stable multi-Gigahertz on-chip clock sources. To meet this need, methods for characterizing and measuring the short-term stability of such sources are required. In this paper we identify the relevant figure of merit to characterize and compare various clocks: the cycle-to-cycle standard deviation of the clock periods. We have developed experimental techniques for the measurement of this figure of merit and applied it to the characterization of an RSFQ ring oscillator. The experimental results are compared with results from a stochastic circuit simulator. We determined the value of jitter to be 1.52% at 10 GHz.
Superconducting digital systems based on Josephson junctions have generally used a synchronous timing strategy. A master clock signal is used to delimit a data window during which the system changes state and data is transferred from one block to the next. The temporal stability of the clock signal has a profound effect on the performance of rapid single flux quantum (RSFQ) digital systems. In particular, short-term clock fluctuations, or clock jitter, can degrade system performance due to the hazard of timing constraint violations. The successful development of large-scale RSFQ digital systems will require highly stable multigigahertz on-chip clock sources. To meet this need, methods for characterizing and measuring the short-term stability of such sources are required. We identify the relevant figure of merit to characterize and compare various clocks: the cycle-to-cycle standard deviation of the clock periods. We present experimental techniques for the measurement of this figure of merit and apply them to the measurement of jitter in a clock generator used often in RSFQ systems, the ring oscillator. High-frequency phase noise measurements found the jitter of a 9.6-GHz clock to be in the range from 0.6% to 0.36% of the clock period. The measured values of clock jitter fell within the 95% confidence interval of our stochastic circuit simulations. This was sufficient evidence to conclude that thermal noise from the resistors in the circuit may be the dominant source of jitter in the ring oscillator.
Stability of Josephson junction clock sources can be a limiting factor in the operation of RSFQ digital and mixed signal circuits. We have developed techniques for the characterization of the short-term stability, i.e., the jitter, of Josephson junction clock sources, and in this paper we present measurements of the jitter for a long Josephson junction soliton oscillator clock. The output frequency of the soliton oscillator was prescaled by using a chain of T flip-flops and using a current bias feedback the oscillator was phase locked to a stable room temperature RP source. Phase noise spectra of the clock signal were measured at the successive stages of the T flip-flop chain and interpreted to infer the cycle-to-cycle jitter of the soliton oscillator. The jitter at the output of the soliton oscillator was measured to be 60 fs at a frequency of 26 GHz, or 0.16% of the period of the clock.
Ring oscillators are the traditional on-chip clock source for RSFQ mixed-signal and digital circuits. Their long-term frequency stability is essential for certain signal processing applications such as the sampling clock for an A/D converter or the output clock of a D/A converter. However conventional bias schemes lead to excessive drift in the frequency. Embedding the ring oscillator in a phase-locked loop (PLL) circuit allows it to inherit the frequency stability of an external reference source. An RSFQ circuit comprised of a ring oscillator, a divide-by-2 20 prescaler and a resynchronizer D flip-flop was fabricated using the standard 1 kA cm -2 niobium foundry service from Hypres. The circuit was stabilized using a low-frequency PLL with a bandwidth of 6 Hz. The output of the phase detector in the PLL was used to produce a feedback current that stabilized the frequency of the ring oscillator at around 8 GHz. The frequency spectrum of the RSFQ scaled oscillator output was measured in open- and closed-loop configurations. Compared to the open-loop phase noise spectrum the closed-loop spectrum showed a decrease of 30 dB of the oscillator phase noise at an offset of 1 Hz from the divided-down carrier frequency of 4.1 kHz. This agreed with the classical phase-locked loop model for the system. The long-term frequency drift of the RSFQ clock was determined by the stability of the oven-controlled quartz oscillator used as the reference in the PLL.
Digital superconducting systems based on Josephson junctions make generally use of the synchronous timing strategy. Today, one of its most promising applications is the high speed and high dynamic range signal sensing. A digital signal acquisition system should have a high resolution as well as a short sampling interval with a well known and constant time period. Short term clock fluctuations (clock jitter) induced by thermal noise can significantly disturb the system operation due to hazards of timing constraint violations. This uncertainty in the time period is currently a strong limitation for further improvements of fast signal sensing systems based on superconductive electronics. Recently, several theoretical and experimental studies describe the timing jitter in simple circuits, like Josephson transmission lines. In the presented work, we analyse different fabrication technologies for rapid single flux quantum (RSFQ) electronics and predict their timing jitter by the numerical solution of stochastic differential equations. We obtained a very good agreement between our simulation data and recent experimental results.
On-chip, high-frequency clock sources are essential for the future development of superconductor digital circuits and systems. We have developed clock sources for rapid single flux quantum (RSFQ) digital circuits using high-quality long Josephson junction (LJJ) resonant oscillators that offer extremely low jitter. To meet the requirement for time-interleaved clock signals of complementary phase, two-phase 30 and 50 GHz clock sources using LJJ's have been developed with both linear and annular geometry. Unperturbed by reflections from boundaries and collisions among the fluxons (flux quanta), the annular LJJ oscillator has demonstrated superior stability and higher quality factor (>10/sup 6/) than the linear LJJ oscillator. The LJJ oscillator with linear geometry is easier to interface with RSFQ circuitry since it has well-defined boundaries at either end, facilitating a two-phase clock source. On the other hand, multiple clock phases may be derived from an annular LJJ oscillator by connecting interface circuitry at various points around the circular junction, if the interface circuitry does not interfere with the fluxon(s) in the annular junction. Experimental results for two-phase RSFQ clock sources based on linear and annular LJJ oscillators are presented.
We have developed clock sources for rapid single flux quantum (RSFQ) digital circuits using high-quality long Josephson junction (LJJ) resonant oscillators of annular geometry. Being a topologically closed system and unperturbed by reflections from boundaries and collisions among the fluxons (flux quanta), the annular LJJ oscillator has demonstrated a high quality factor. The novel design of an annular junction clock that allows easier interface with RSFQ circuitry has been realized. Magnetic fluxons are inserted into an annular LJJ by local injection of current into the control line of the junction. This technique resolves the long-standing problem of achieving superior stability of the fluxon state for application as a clock source. The linewidth of the phase-locked clock source is measured as low as 24 Hz relative to a reference oscillator at 40 GHz. The cycle-to-cycle jitter was measured to be 9 fs at a frequency of 36 GHz, or 0.04% of the clock period which is in good agreement with theoretical estimation.