We present additional RSFQ superconductive digital electronics logic gates that have been developed to complement already existing gates. These gates are the NOR, NAND and XNOR. The gates were designed, simulated and laid out for fabrication in both IPHT's FLUXONICS 1 kA/cm2and Hypres’ 4.5 kA/cm2processes. Layout circuit parameters such as inductance were extracted to compare these with design values. Good working margins were obtained after several steps of manual circuit optimisation during the design and simulation stages. NioPulse, superconductor circuit design software developed by NioCAD in South Africa, was used and evaluated during the design process.
We present additional RSFQ superconductive digital electronics logic gates that have been developed to complement already existing gates. These gates are the NOR, NAND and XNOR. The gates were designed, simulated and laid out for fabrication in both IPHT's FLUXONICS 1 kA/cm2and Hypres’ 4.5 kA/cm2processes. Layout circuit parameters such as inductance were extracted to compare these with design values. Good working margins were obtained after several steps of manual circuit optimisation during the design and simulation stages. NioPulse, superconductor circuit design software developed by NioCAD in South Africa, was used and evaluated during the design process.
ENGLISH ABSTRACT: Rapid Single Flux Quantum (RSFQ) cells are key in the design of complex and applicable RSFQ electronic circuits. These cells are low-level circuit elements that are used repeatedly to build larger, applicable RSFQ circuitry. Making these cells simple to layout and manufacture, but reliable for extensive use demands a careful development process for RSFQ cells. Cell functionality is verified through simulations, thereafter the cell is laid out in special software packages. Inductance of on-chip superconductor structures is extracted through careful modelling with numerical field solver software. A cell library has been developed by incorporating existing or published cells after further analysis and optimization, as well as developing new cells. Cells that have been adapted into the library include the Josephson transmission line (JTL), Splitter, Merger, D-Flip Flop (DFF), T-Flip Flop (TFF), NOT, AND, OR and XOR, DC-SFQ and SFQ-DC and PTL Driver and Receivers. New cells include NOR, NAND and XNOR. The cells were designed for the IPHT’s RSFQ1D 1kA/cmª and Hypres’ 4.5kA/cmª processes. The cells in the library have good bias current operating margins obtained through simulations (> ±26%). All cells have all the parameters listed in the thesis including extracted inductance values. In order to have a complete and verified RSFQ cell library, cells have been sent for fabrication at IPHT and Hypres facilities. These cells can now be tested on-chip, in the laboratory, to establish functionality and practical bias current margins. All test signal patterns and bias currents required for testing are defined to allow co-workers or collaborators to test the cells.
The development of an RSFQ cell library for the world's fastest superconducting digital family is hereby presented. Cells ranging from the basic JTL to the more complex NOR gate were laid out and are ready for fabrication. In addition, cell parameters were carefully estimated and inductance extracted using special software tools. To ensure that the cells work with known parameter margins, on-chip testing of these cells are done in the laboratory. Cells ready for fabrication include the JTL, Splitter, Merger, PTL Driver and Receiver, T-flip flop, D-flip flop, OR, NOR, AND, XOR and the NOT, with the XNOR and NAND to be developed next. We discuss test steps and verification of the cells.
We have developed a cell library for superconducting large scale integrated (LSI) digital circuits based on Single Flux Quantum (SFQ) devices. The circuits were designed for a 6-kA/cm2Nb/AlOx/Nb junction process with 10 mask levels including one ground plane and two Nb wiring layers. The initial design and optimization of the circuit parameters were achieved by means of the optimization functions in a circuit simulator, PSCAN2, to ensure that important circuit parameters, Josephson critical current (IC), bias current (Ibias), and inductance satisfied minimal margin requirements. Critical margins of ICand Ibiaswere then further improved manually. To compensate the scattering in the circuit parameters from fabrication by design as much as possible, the critical junction parameters were optimized to further centralize the IC. The library cells were laid out following our design rules determined by systematic experiments on process control monitors (PCM). Basic cells including Josephson transmission lines, splitters, confluence buffers, D flip-flops, T flip-flops, and XOR and NDRO gates were designed, fabricated, and successfully tested at low frequencies. Wide overlaps of the operating regions for the common bias voltages were confirmed.
Superconductor digital technology based on Rapid Single Flux Quantum logic (RSFQ) offers more than 50 times gain in speed and more than 100 reduction in power consumption over mainstream CMOS devices. However, the necessity of cooling down to 4 K and modest degree of integration density currently available mean that employing RSFQ is reasonable only for the tasks that are impossible or ineffective to implement in CMOS technology. One of the promising applications of the RSFQ technology is Digital Signal Processing (DSP) for telecommunications. Interference cancellation is a bottleneck for all existing systems in terms of the performance gain that is theoretically possible and technically realizable using conventional technology. The crucial factor is computational complexity required to handle multiple access interference. The general approach is to compute the interference using available data about propagation channels and then either remove it from received signal or use to predistort the transmitted signal. Computation of the interference matrix can easily fall into 100 Gops range, furthermore, the most e±cient algorithms are based on successive iterations. This requires not only high overall performance of the DSP but also high actual clock rate.This thesis reports a proposed architecture of an RSFQ Successive Interference Canceller and a design of an RSFQ Digital Signal Processor based on hybrid RSFQ-CMOS memory suitable for a general matrix on matrix multiplication algorithm. The processor consists of an RSFQ Multiply-Accumulate Unit, memory caches and a synchronization block, partitioned into multiple chips, and a large CMOS memory.The complexity of the RSFQ DSP is 10x10 multiplication, rounding to 14 bits, 18 bits accumulator length and 3.7 Kb memory cache. In order to implement the RSFQ DSP, we have developed approach to simulate and describe the RSFQ circuits using VHDL. The maximum simulated clock frequency is equal to 24 GHz for Hypres 4.5 kA/cm2 process and optimum communication bandwidth with CMOS memory is 2 Gbps.Components of the processor such as 4x4 two's complement and 5x5 parallel multipliers, 4x5, 20x5 and 4x15 parallel shift registers, a 5-bit serial adder have been designed and experimentally tested. The simplified version of the RSFQ DSP consisting of a 4x4 MAC with rounding to 5 bits and 17x6 memory caches has been designed for Hypres 4.5 kA/cm2 process and fabricated.
Rapid single flux quantum (RSFQ) logic is a digital circuit technology that in recent years has presented itself as an alternative to semiconductors in the application of ultra high speed, very low power applications. The optimal timing of digital circuits operating at hundreds of GHz is still a complex problem for both RSFQ and semiconductor technologies. The fact that most RSFQ gates require a clock signal to function makes this even more complex. Various RSFQ timing schemes have been adapted from semiconductor design methodologies, and some have been designed specifically for RSFQ. Currently, synchronous clocking schemes outperform other schemes, but with the scale of RSFQ circuits ever increasing, the proper use of timing schemes are becoming more crucial. This paper describes a new asynchronous self-timing scheme where the details of clock distribution and clocking are built into the logic gates. Tests were done on the newly developed asynchronous logic gates and an asynchronous full adder was implemented and tested
Abstract\nThis diploma work is about Rapid Single Flux Quantum (RSFQ) circuits. This\nsupercoducting digital circuitry has the most promising properties in terms of speed and\npower consumption. The active elements of the RSFQ circuits are Josephson junctions (JJ).\nFor their fabrication low temperature superconducting niobium films are used. Today the\ndesign and fabrication of RSFQ circuits are done in a standardized way with well-defined\ndesign rules. Nevertheless, to design complicated circuits with more than several hundred\njunctions a lot of practical problems must be solved.\nDifferent aspects of the RSFQ circuits design process were investigated in this work.\nIn the theoretical part we propose a new, more realistic model of the Josephson junction for\nphysical simulation (which is necessarily used for design of every RSFQ gate) in order to\nimprove its quality and precision. The new model for the JJ includes additional inductances,\nwhich must reflect a specific environment of the junction layout. The influence of parameter\ndeviations was investigated in the simulation. As sources of the deviation we chose the\nspread of c (the Stewart-McCumber parameter) and that of the inductances. Then the\noperational margins of the basic elements of the RSFQ logic SR flip-flop were determined\nand compared with the prediction of the previously used model. To prove the results of\nsimulations we designed a test structure of the SR flip-flop, with c=1 and c=2 for the wellestablished\nHYPRES technology (USA).\nAnother part of the work is practical measurements. A test chip, containing chains of 100\nJosephson junctions was designed and measured in order to estimate the spread of critical\ncurrents in real technology.