Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

IEEE Transactions on Applied Superconductivity

A low power 12 bit flux shuttle shift register with Nb technology

R. Lochschmied, R. Herwig, M. Neuhaus, W. Jutzi

Published Jun 1, 1997• 14 citations
Publisher

Abstract

A 12 bit Flux Shuttle shift register with a new write and readout gate has been simulated and fabricated using Nb/Al/sub 2/O/sub 3//Nb Josephson junctions. Write, shift and read operations have been tested successfully at 4.2 K. Drive currents are independent from input bit sequence. Although measurements were disturbed by trapped flux, minimum margins are /spl Delta/I=/spl plusmn/10%. The power dissipation of a shift register cell is 9 nW/GHz. Total power losses caused by terminating resistors are 70 /spl mu/W. The minimum line width may be scaled down to 0.5 /spl mu/m, because power losses per unit area of long Flux Shuttle shift registers are extremely low.

DOI
10.1109/77.621945

Related papers

Design and testing of rapid single flux quantum shift registers with magnetically coupled readout gates

Perng-Fei Yuh, Oleg A. Mukhanov

Experimental superconducting shift registers consisting of on-chip clock generators, clock regeneration and distribution circuits, shift register elements, and readout circuits are designed using rapid single flux quantum logic/memory (RSFQ) gates. A 7-b shift register has been tested to 12 GHz and a 17-b to 21 GHz using external triggering clocks with relative delay measurements. Testing with internal clocks generated from Josephson oscillations shows a potential high-speed operation of 45 GHz for the 7-b and 30 GHz for the 17-b shift registers. Two types of magnetically coupled readout gates are discussed. The chips are fabricated using a Nb/AlO/sub /x/Nb Josephson-junction process at a critical-current density of 1000 A/cm/sup 2/. The power dissipation per bit is 3 mu W.>

IEEE Transactions on Applied Superconductivity•Jan 1, 1992•21 citations

A 512-bit shift register using compact two-phase single flux quantum clock generators with large margins and low power

Perng-Fei Yuh

A 512-b shift register was built and tested up to 14.5 GHz. The shift register uses a two-phase clock which is generated by coupling a master control line over many asymmetrically biased two-junction SQUIDs. Compared with other shift registers with Josephson transmission lines to deliver clock, this new clock system provides short delay, low power dissipation, and large DC bias margins. The shift register uses about 3000 Nb/AlO/sub x//Nb Josephson junctions and consumes about 0.1 mW.>

IEEE Transactions on Applied Superconductivity•Jan 1, 1993•2 citations

Superconducting Shuttle-flux Shift Buffer for Race Logic

Meriam Gay Bautista, Patricia Gonzalez-Guerrero, Darren Lyles +1 more

This paper presents a superconducting magnetically coupled shift buffer based on a shuttle-flux shift register that stores single flux quantum (SFQ) pulses. The shift register has a DC bias operating margin of ±34% at 10 GHz, the power dissipation of 3.6µW at the clock bias, and 38% fewer Josephson junctions for 1024 stages compared to DFF-based shift registers. Clock bias is independent of the input pulse sequence through inductive coupling with a minimal current drive. Based on our shift register, we add two non-destructive readouts (NDRO) cells to construct a buffer that can inexpensively store the temporal information of race logic (RL) pulses or a pulse train for spiking neural networks. These applications motivate deep shift registers with many shifting intervals, which our shift register can implement with only a pair of coupled inductors and one JJ per shifting interval.

IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)•Aug 9, 2021•4 citations

A 4 bit YBa/sub 2/Cu/sub 3/O/sub 7-δ/ bicrystal Josephson junctions flux shuttle shift register

R. Koch, Theo Andreas Scherer, M. Winter +1 more

A flux shuttle shift register with master and slave sections is implemented with YBCO Josephson junctions along only one straight grain boundary of a bicrystal substrate. The investigated prototype comprises a write circuit, four master/slave shift register cells and a dynamic read out circuit for single flux quanta. The simulation results and the layout are presented.

IEEE Transactions on Applied Superconductivity•Jun 1, 1997•6 citations

Operation of a 64-bit superconducting shift register at 8 GHz

Perng-Fei Yuh

A 64 b superconducting shift register based on edge-triggered gates has been tested up to 8.45 GHz with two-phase sine wave clocks. The edge-triggered gates are made by serial connection of a Josephson junction and a modified variable threshold gate, fabricated by an Nb-AlO/sub x/-Nb process. Wide operating margins and simple two-phase clocks make this shift register relatively easy to test. Power dissipation is 10 mu W/b.>

IEEE Transactions on Applied Superconductivity•Mar 1, 1993•1 citation

Performance issues in single flux quantum shift registers

J.H. Hang, John X. Przybysz

Testing on a single-flux-quantum (SFQ) shift register fabricated with a SFQ Nb-AlO/sub x/Nb Josephson junction process indicates that a stable flux quantum can be stored in a rapid SFQ (RSFQ) shift register stage and be shifted by SFQ pulses. Design simulations showed that logic errors can occur in SFQ shift registers even though the circuit passes the average voltage test. Three-junction-per-stage shift registers had an advantage over the two-junction-per-stage shift register in handling data with successive 1's and in incorporating resistors to increase tolerance of trapped magnetic flux. Input and output buffers for data and clock pulses were added to get an RSFQ shift register to obtain correct performance. The highest error-free operation speed for the data with successive 1's is about half of the speed for propagation of a lone data 1. Error-free operation of SFQ shift registers with three junctions per stage could be obtained up to speeds of 30-60 GHz with Josephson junctions having I/sub c/R/sub n/ (critical-current-normal-resistance product) values of 600 mu V.>

IEEE Transactions on Applied Superconductivity•Mar 1, 1993•8 citations
A 12 bit Flux Shuttle shift register with a new write and readout gate has been simulated and fabricated using Nb/Al/sub 2/O/sub 3//Nb Josephson junctions. Write, shift and read operations have been tested successfully at 4.2 K. Drive currents are independent from input bit sequence. Although measurements were disturbed by trapped flux, minimum margins are /spl Delta/I=/spl plusmn/10%. The power dissipation of a shift register cell is 9 nW/GHz. Total power losses caused by terminating resistors are 70 /spl mu/W. The minimum line width may be scaled down to 0.5 /spl mu/m, because power losses per unit area of long Flux Shuttle shift registers are extremely low.
Experimental superconducting shift registers consisting of on-chip clock generators, clock regeneration and distribution circuits, shift register elements, and readout circuits are designed using rapid single flux quantum logic/memory (RSFQ) gates. A 7-b shift register has been tested to 12 GHz and a 17-b to 21 GHz using external triggering clocks with relative delay measurements. Testing with internal clocks generated from Josephson oscillations shows a potential high-speed operation of 45 GHz for the 7-b and 30 GHz for the 17-b shift registers. Two types of magnetically coupled readout gates are discussed. The chips are fabricated using a Nb/AlO/sub /x/Nb Josephson-junction process at a critical-current density of 1000 A/cm/sup 2/. The power dissipation per bit is 3 mu W.>
This paper presents a superconducting magnetically coupled shift buffer based on a shuttle-flux shift register that stores single flux quantum (SFQ) pulses. The shift register has a DC bias operating margin of ±34% at 10 GHz, the power dissipation of 3.6µW at the clock bias, and 38% fewer Josephson junctions for 1024 stages compared to DFF-based shift registers. Clock bias is independent of the input pulse sequence through inductive coupling with a minimal current drive. Based on our shift register, we add two non-destructive readouts (NDRO) cells to construct a buffer that can inexpensively store the temporal information of race logic (RL) pulses or a pulse train for spiking neural networks. These applications motivate deep shift registers with many shifting intervals, which our shift register can implement with only a pair of coupled inductors and one JJ per shifting interval.
Testing on a single-flux-quantum (SFQ) shift register fabricated with a SFQ Nb-AlO/sub x/Nb Josephson junction process indicates that a stable flux quantum can be stored in a rapid SFQ (RSFQ) shift register stage and be shifted by SFQ pulses. Design simulations showed that logic errors can occur in SFQ shift registers even though the circuit passes the average voltage test. Three-junction-per-stage shift registers had an advantage over the two-junction-per-stage shift register in handling data with successive 1's and in incorporating resistors to increase tolerance of trapped magnetic flux. Input and output buffers for data and clock pulses were added to get an RSFQ shift register to obtain correct performance. The highest error-free operation speed for the data with successive 1's is about half of the speed for propagation of a lone data 1. Error-free operation of SFQ shift registers with three junctions per stage could be obtained up to speeds of 30-60 GHz with Josephson junctions having I/sub c/R/sub n/ (critical-current-normal-resistance product) values of 600 mu V.>