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IEEE Transactions on Applied Superconductivity

Automatic Josephson-transmission-line routing for single-flux-quantum cell-based logic circuits

Y. Kameda, Shinichi Yorozu

Published Jun 1, 2003• 8 citations
Publisher

Abstract

In single-flux-quantum (SFQ) circuits, the delay produced by the Josephson transmission line (JTL) is comparable with or larger than the one produced by the logic cells. Therefore, it is difficult to find the routes that satisfy the timing constraints in a large circuit manually. To overcome this obstacle, we propose a two-step automatic JTL routing technology that performs coarse and fine timing adjustments. First, an automatic router draws dummy wires within coarse timing constraints, and then the dummy wires are replaced with JTL cells. Fine timing adjustments are done in the latter step. Some JTL cells in clock and data paths are replaced with faster JTL cells so that clock signals always arrive earlier than data signals at clocked-gates. Two example circuits were designed using the automatic JTL routing technology. One is composed of nearly 600 Josephson junctions. It was experimentally tested up to 35 GHz with on-chip test components. The other is composed of about 4000 Josephson junctions. After the fine timing adjustment, logic simulation showed that it can operate at 20 GHz. We also experimentally confirmed its correct operations at low speed.

DOI
10.1109/tasc.2003.813922

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IEEE Transactions on Applied Superconductivity•Jun 1, 2005•12 citations
In single-flux-quantum (SFQ) circuits, the delay produced by the Josephson transmission line (JTL) is comparable with or larger than the one produced by the logic cells. Therefore, it is difficult to find the routes that satisfy the timing constraints in a large circuit manually. To overcome this obstacle, we propose a two-step automatic JTL routing technology that performs coarse and fine timing adjustments. First, an automatic router draws dummy wires within coarse timing constraints, and then the dummy wires are replaced with JTL cells. Fine timing adjustments are done in the latter step. Some JTL cells in clock and data paths are replaced with faster JTL cells so that clock signals always arrive earlier than data signals at clocked-gates. Two example circuits were designed using the automatic JTL routing technology. One is composed of nearly 600 Josephson junctions. It was experimentally tested up to 35 GHz with on-chip test components. The other is composed of about 4000 Josephson junctions. After the fine timing adjustment, logic simulation showed that it can operate at 20 GHz. We also experimentally confirmed its correct operations at low speed.
We have been developing a single-flux-quantum (SFQ) cross-bar switch, which is a main component of a network packet switch. We think that a network switch is an application in which the high speed of SFQ technology would be advantageous. Anticipating general and large-scale SFQ logic circuit design, we used the cell-based design method and the CONNECT standard SFQ cell library. The two-input and two-output cross-bar switch, a core switch component, consists of 13 logic cells connected by Josephson-transmission-line (JTL) cells. Because of the large size of JTL cells and the large delay in them, timing adjustment becomes more difficult as the operating speed and circuit size increase. After using a commercially available automatic router to find appropriate routes efficiently, we used a static timing analyzer for fine timing adjustment. Timing violations were fixed by changing JTL path delays using the tools we developed. The target operating frequency of the switch was 40 GHz, which corresponds to a clock period of 25 ps. Careful timing adjustment was necessary to ensure correct operations at such a high speed. The test chip was fabricated by using an NEC standard Nb process. The circuit, including on-chip test circuitry, was composed of about 1500 Josephson junctions. We confirmed its correct operations up to 50 GHz with a bias margin of /spl plusmn/20%.
The introduction of passive-transmission-line (PTL) wiring to large-scale SFQ logic circuits offers several advantages over traditional Josephson-transmission-line (JTL) wiring, such as smaller wiring area, less delay, lower power consumption, and more freedom in routing. PTL wiring can drastically change the style of designing SFQ logic circuits. We propose a new methodology for designing large-scale SFQ circuits using PTL wiring. Aiming at generalizing SFQ circuit design, we chose synchronous clocking. We developed a placer that was suitable for SFQ circuit design to assist us with the new design methodology. The placer first synthesizes an H-tree clock distribution network, placing SFQ pulse splitter cells at each branch. It then places logic cells to minimize the maximum length of data PTL wires, aiming at higher operating speeds. Finally, a router completes the PTL wiring. To evaluate the design methodology we designed an 8-bit general purpose RISC processor. Within twelve hours, we obtained a 15-mm-square SFQ circuit that could operate up to 27.6 GHz. We adopted an advanced Nb process, which was characterized by a critical current density of 10 kA/cm2, two 5-mum-wide PTL wiring layers, and a minimum cell size of 30 mum times 30 mum. The circuit consisted of about 20,000 logic cells, which approximated more than 400,000 Josephson junctions including splitters to distribute the clock signal.
An automated layout design flow for rapid single-flux-quantum circuits is proposed in this article. In order to realize small circuit area and low latency, both Josephson transmission lines (JTLs) and passive transmission lines (PTLs) are used for interconnects. Placement and routing are performed considering effective use of JTLs and PTLs. Logic cells are grouped into clusters, and JTLs are used inside clusters. PTLs are used among clusters. The placement process is composed of three steps: first, cell clustering, second, cell placement and JTL routing in each cluster, and third, cluster placement. After the placement process, routing among clusters are performed using PTLs. We applied the proposed design flow to sample circuits with several hundreds of gates. Though the circuit area is not fully optimized, the latency of the circuits designed by the proposed design flow are lower than those of the circuits designed manually.
We have developed a method of designing single-flux-quantum (SFQ) logic circuits with passive gate-to-gate interconnections. Based on our method, we designed a 2/spl times/2 switch in which all the interconnections are implemented with passive transmission lines (PTLs) while short Josephson transmission line (JTL) segments are used only to adjust the signal timings. Compared with an identical switch using JTL interconnections, the switch using PTL interconnections has 45% fewer wiring junctions and requires 48% less wiring power current. The switch operated at 40 GHz with a bias margin of /spl plusmn/9.5%.
We demonstrated an automated passive-transmission-line routing tool for single-flux-quantum (SFQ) circuits. The tool is based on the A* algorithm, which is widely used in CMOS LSI design, and tuned for microstrip/strip lines formed in the SRL 4-Nb layer structure. In large-scale SFQ circuits with 10000-20000 Josephson junctions, such as microprocessors, 80-90% of the wires can be automatically routed in about ten minutes. We verified correct operation above 40GHz for an automatically routed 4 × 4 switch circuit from on-chip high-speed tests. The resulting circuit size and operating frequency were comparable to those of a manually designed result. We believe that the tool is useful for large-scale SFQ circuit design using conventional fabrication processes.
Timing jitter is an important constraint for the performance of SFQ circuits. We focus on the timing jitter in a Josephson transmission line (JTL) that induces timing errors at logic gates. A proper data analysis of 2-bit shift registers gave a jitter value of about 0.08 ps for a single Josephson junction in a JTL powered at a designed bias current. The variations in timing parameters of logic cells also give rise to timing errors. We experimentally determined the timing parameters in several logic cells and found that the deviations between actual and nominal values are within 2 ps. The relationship between the gray zone and circuit scale was estimated by extrapolating the transition curves observed in 2-bit shift registers. The estimated circuit scale was 20,000-100,000 JJs and 1,000 JJs at an operating clock frequency of 20 GHz and 40 GHz, respectively.