We demonstrated an automated passive-transmission-line routing tool for single-flux-quantum (SFQ) circuits. The tool is based on the A* algorithm, which is widely used in CMOS LSI design, and tuned for microstrip/strip lines formed in the SRL 4-Nb layer structure. In large-scale SFQ circuits with 10000-20000 Josephson junctions, such as microprocessors, 80-90% of the wires can be automatically routed in about ten minutes. We verified correct operation above 40GHz for an automatically routed 4 × 4 switch circuit from on-chip high-speed tests. The resulting circuit size and operating frequency were comparable to those of a manually designed result. We believe that the tool is useful for large-scale SFQ circuit design using conventional fabrication processes.
We demonstrated an automated passive-transmission-line routing tool for single-flux-quantum (SFQ) circuits. The tool is based on the A* algorithm, which is widely used in CMOS LSI design, and tuned for microstrip/strip lines formed in the SRL 4-Nb layer structure. In large-scale SFQ circuits with 10000-20000 Josephson junctions, such as microprocessors, 80-90% of the wires can be automatically routed in about ten minutes. We verified correct operation above 40GHz for an automatically routed 4 × 4 switch circuit from on-chip high-speed tests. The resulting circuit size and operating frequency were comparable to those of a manually designed result. We believe that the tool is useful for large-scale SFQ circuit design using conventional fabrication processes.
In single-flux-quantum (SFQ) circuits, the delay produced by the Josephson transmission line (JTL) is comparable with or larger than the one produced by the logic cells. Therefore, it is difficult to find the routes that satisfy the timing constraints in a large circuit manually. To overcome this obstacle, we propose a two-step automatic JTL routing technology that performs coarse and fine timing adjustments. First, an automatic router draws dummy wires within coarse timing constraints, and then the dummy wires are replaced with JTL cells. Fine timing adjustments are done in the latter step. Some JTL cells in clock and data paths are replaced with faster JTL cells so that clock signals always arrive earlier than data signals at clocked-gates. Two example circuits were designed using the automatic JTL routing technology. One is composed of nearly 600 Josephson junctions. It was experimentally tested up to 35 GHz with on-chip test components. The other is composed of about 4000 Josephson junctions. After the fine timing adjustment, logic simulation showed that it can operate at 20 GHz. We also experimentally confirmed its correct operations at low speed.
The introduction of passive-transmission-line (PTL) wiring to large-scale SFQ logic circuits offers several advantages over traditional Josephson-transmission-line (JTL) wiring, such as smaller wiring area, less delay, lower power consumption, and more freedom in routing. PTL wiring can drastically change the style of designing SFQ logic circuits. We propose a new methodology for designing large-scale SFQ circuits using PTL wiring. Aiming at generalizing SFQ circuit design, we chose synchronous clocking. We developed a placer that was suitable for SFQ circuit design to assist us with the new design methodology. The placer first synthesizes an H-tree clock distribution network, placing SFQ pulse splitter cells at each branch. It then places logic cells to minimize the maximum length of data PTL wires, aiming at higher operating speeds. Finally, a router completes the PTL wiring. To evaluate the design methodology we designed an 8-bit general purpose RISC processor. Within twelve hours, we obtained a 15-mm-square SFQ circuit that could operate up to 27.6 GHz. We adopted an advanced Nb process, which was characterized by a critical current density of 10 kA/cm2, two 5-mum-wide PTL wiring layers, and a minimum cell size of 30 mum times 30 mum. The circuit consisted of about 20,000 logic cells, which approximated more than 400,000 Josephson junctions including splitters to distribute the clock signal.
The increasing complexity of modern rapid single flux quantum (RSFQ) circuits has made on-chip signal routing, an issue of growing importance. In this paper, several methods for routing large-scale RSFQ circuits are described, and a process is presented for determining when to use passive microstrip transmission lines (PTL) and active Josephson transmission lines (JTL). The effect of the size of the JTL inductor and Josephson junctions on the length of a JTL chain for a target delay is also discussed. The dependence of the JTL inductance on the physical layout is evaluated, and the effects of the primary PTL parameters on delay are characterized. A novel PTL driver and receiver configuration is also proposed. Tradeoffs among the number of JJs, inductance, and length of a PTL stripline in the receiver and driver circuits are reported. The energy dissipation is evaluated for two different interconnects. A tradeoff between the proposed PTL circuits and an optimized JTL in terms of energy dissipation and delay is discussed. Guidelines for choosing the optimal element values are determined, and a simulated bias margin of ±29% for the bias current of the proposed receiver operating at 20 GHz in a 10 kA/cm2technology for a 1-mm transmission line is achieved. Summarizing, guidelines and design tradeoffs appropriate for automated layout and synthesis are provided for driving long interconnect in SFQ VLSI circuits.
We have been developing a single-flux-quantum (SFQ) cross-bar switch, which is a main component of a network packet switch. We think that a network switch is an application in which the high speed of SFQ technology would be advantageous. Anticipating general and large-scale SFQ logic circuit design, we used the cell-based design method and the CONNECT standard SFQ cell library. The two-input and two-output cross-bar switch, a core switch component, consists of 13 logic cells connected by Josephson-transmission-line (JTL) cells. Because of the large size of JTL cells and the large delay in them, timing adjustment becomes more difficult as the operating speed and circuit size increase. After using a commercially available automatic router to find appropriate routes efficiently, we used a static timing analyzer for fine timing adjustment. Timing violations were fixed by changing JTL path delays using the tools we developed. The target operating frequency of the switch was 40 GHz, which corresponds to a clock period of 25 ps. Careful timing adjustment was necessary to ensure correct operations at such a high speed. The test chip was fabricated by using an NEC standard Nb process. The circuit, including on-chip test circuitry, was composed of about 1500 Josephson junctions. We confirmed its correct operations up to 50 GHz with a bias margin of /spl plusmn/20%.
Superconductive electronics based on Josephson junctions (JJ) is a promising cryogenic alternative technology to complementary metal oxide semiconductor (CMOS) technology for ultra-low energy, high speed stationary applications. For complex superconductive systems, the automated routing process determines the topology and methodology to connect cells while satisfying design constraints. On-chip signal routing has become an issue of growing importance in modern superconductive technologies; particularly, single flux quantum (SFQ) systems. Specialized routing methods for these systems are required. These routing methods include passive transmission lines (PTLs) and Josephson transmission lines (JTLs) behaving as interconnects. A primary issue within a long SFQ interconnect is the effects of resonance due to the imperfect match between the PTLs and Josephson junctions. A repeater insertion methodology to reduce and manage these resonance effects is required for driving long and short interconnect in VLSI complexity SFQ systems. Permissible interconnect lengths are suggested to ensure the reflections do not affect the returning signals. The microwave behavior of the interconnect striplines is also considered to accurately estimate the surface inductance of the lines. A closed-form expression describing the dependence of the surface inductance of a stripline on the line thickness, magnetic field, and current density is discussed. Another primary issue within SFQ circuits is coupling noise between transmission striplines, degrading performance and decreasing margins. Inductive and capacitive coupling noise between the routing layers, for the MIT LL SFQ5ee process, is described. An analysis of inductive and capacitive coupling noise can determine the minimum physical spacing between lines to enhance the automated routing process in large scale systems. The increasing complexity of modern SFQ circuits has also made the issue of flux trapping of growing importance. The use of wide striplines for signal routing has exacerbated this issue. Trapped residual magnetic fields within the striplines damage the operability of superconductive circuits. Area efficient topologies for striplines are introduced to manage flux trapping in large scale SFQ circuits. These topologies are composed of several narrow lines rather than a single wide stripline. The first approach is a narrow parallel line topology in series with small resistors where each narrow line is connected to a single small resistor and via. The resistors in the parallel line topology remove any trapped fluxons and break any loops while requiring additional vias. The second topology is a fingered narrow line topology. The fingered narrow line topology enhances the scalability of SFQ systems while not requiring additional area and vias. These proposed topologies require significantly less area while preventing flux from being trapped within wide superconductive striplines and reducing coupling noise between striplines. These methodologies and techniques are intended as guidelines to enable robust routing with superconductive interconnects. With these and other advances in design methodologies for superconductive electronics, the complexity of SFQ circuits is expected to greatly increase.
We have developed a very flexible wiring technique of passive transmission lines (PTLs) in single-flux-quantum (SFQ) circuits. For high flexibility, we introduced two types of wiring structures of strip lines (SLs) and microstrip lines (MSLs) using the fabrication process which has four metal layers. The SLs and MSLs are realized using the second and fourth metal layers as signal lines, respectively, from the bottom (the other two metal layers are used as ground planes). We also introduced via-holes for transmission between the SL and MSL. For solving the problem of impedance mismatch on complicated discontinuous sections such as joints [between the driver(receiver) and the end of SLs(MSLs)] and via-holes, we optimized the structures of these discontinuous sections and evaluated propagation properties to ensure high-speed transmission of SFQ pulses. We tested the transmission of SFQ pulses through SLs/MSLs including more than 50 via-holes, one of the most complicated lines in actual designs. We confirmed the good propagation properties of SFQ pulses up to 50 Gb/s with sufficiently wide bias margins of ±20% to be used in practical designs.