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Conference proceedings - Canadian Conference on Electrical and Computer Engineering

On using FPGAS to accelerate the emulation of quantum computing

Tamer Mohamed, Wael Maged Badawy, GRAHAM A. JULLIEN

Published May 1, 2009• 4 citations
Publisher

Abstract

This paper investigates the possibility of implementing a conventional computing architecture that can practically emulate the functionality of a hypothetical quantum computer. The state of the art transistor feature size makes the resource requirement, for emulating quantum computation with a relatively large number of qubits, possible. In this paperwe investigate how a programmable logic array can be used to practically emulate quantum computation with entanglement characteristics. We illustrate the concept of our practical quantum computer emulator by examining the steps required to build a HW/SW co-design system that can automatically instantiate HW components that implement a quantum computing processing step.

DOI
10.1109/ccece.2009.5090115

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This paper investigates the possibility of implementing a conventional computing architecture that can practically emulate the functionality of a hypothetical quantum computer. The state of the art transistor feature size makes the resource requirement, for emulating quantum computation with a relatively large number of qubits, possible. In this paperwe investigate how a programmable logic array can be used to practically emulate quantum computation with entanglement characteristics. We illustrate the concept of our practical quantum computer emulator by examining the steps required to build a HW/SW co-design system that can automatically instantiate HW components that implement a quantum computing processing step.
Hardware emulation of quantum systems can mimic more efficiently the parallel behaviour of quantum computations, thus allowing higher processing speed-up than software simulations. In this paper, an efficient hardware emulation method that employs a serial-parallel hardware architecture targeted for field programmable gate array (FPGA) is proposed. Quantum Fourier transform and Grover’s search are chosen as case studies in this work since they are the core of many useful quantum algorithms. Experimental work shows that, with the proposed emulation architecture, a linear reduction in resource utilization is attained against the pipeline implementations proposed in prior works. The proposed work contributes to the formulation of a proof-of-concept baseline FPGA emulation framework with optimization on datapath designs that can be extended to emulate practical large-scale quantum circuits.
Quantum computer emulators implemented on FPGA are generally designed to illustrate possible applications in which these concepts can be used - as a method of functional testing of possible applications involving quantum computing. In this paper we try to present another possible use of a quantum computation emulator, proposed by the authors, for the synthesis of circuits in FPGA with superior performance to conventional or parallel design methods. The paper presents a synthesis solution of parallel structures based on concepts from quantum computation emulated on FPGA. As will be seen in the paper, using the solution improves the computation time compared to the conventional method and reduces the number of resources allocated compared to the parallel solution. So, the solution which we propose is somewhere between conventional sequential logic circuit design methods - it has a shorter response time than these and parallel circuit design methods - it provides a smaller number of resources than these. In order to show the advantages of the proposed solution, we presented the implementation of a circuit for determining the parity of a binary function. The solution was implemented using the conventional solution, the parallel solution and the proposed solution using quantum computing concepts. It will show the performance of the proposed solution compared to the other design models.
Quantum hardware emulators using field programmable gate arrays (FPGAs) have been demonstrated to efficiently exploit the inherent parallelism of quantum algorithms and perform better than sequential software simulators. However, one key problem in mapping quantum circuits on FPGAs is the exponential increase in resource requirements with the increase in the number of quantum bits (qubits). As a result, the precision of hardware emulators is often reduced to save resources and accommodate larger quantum circuits which results in lower accuracy and lower throughput. In this paper, we present a full precision FPGA quantum emulator that uses 32-bit floating-point arithmetic and has a fully pipelined architecture. Our emulator is capable of emulating an entangled 4-qubit quantum system performing Quantum Fourier Transform, Grover's Search algorithms on a single FPGA node. Our experimental work was conducted on a highly scalable multi-node (multi-FPGA) state-of-the-art high-performance reconfigurable computer (HPRC). Experimental results show that our emulator is functionally accurate and has a higher operating frequency relative to other emulators. For emulating larger-scale circuits we propose using a multi-node architecture scheme with low latency, high bandwidth inter-node communication.
As quantum computers of non-trivial size become available in the near future, it is imperative to develop tools to emulate small quantum computers. This allows for validation and debugging of algorithms as well as exploring hardware-software co-design to guide the development of quantum hardware and architectures. The simulation of quantum computers entails multiplications of sparse matrices with very large dense vectors of dimension 2n, where n denotes the number of qubits, making this a memory-bound and network bandwidth-limited application. We introduce the concept of a quantum computer emulator as a component of a software framework for quantum computing, enabling a significant performance advantage over simulators by emulating quantum algorithms at a high level rather than simulating individual gate operations. We describe various optimization approaches and present benchmarking results, establishing the superiority of quantum computer emulators in terms of performance.
Abstract The number of transistors per unit area are increasing every year by virtue of Moore’s law. It is estimated that the current rate of evolution in the field of chip design will reduce the transistor to atomic scale by 2024. At atomic level the quantum mechanical characteristics dominate, affecting the ability of transistors to store information in the form of bits. The quantum computers have been proposed as one way to effectively deal with this predicament. The quantum computing circuits utilize the spinning characteristics of electron to store information. This paper describes a proposition of resource efficient FPGA based quantum circuit abstraction. A non-programmable embedded system capable of storing, introducing a phase shift in the qubit and its measurement is implemented. The main objective of the proposed abstraction is to provide a FPGA based platform comprising of fundamental sub blocks for designing quantum circuits. A primary quantum key distribution algorithm i.e BB84 is implemented on the proposed platform as a proof of concept. The distinguishing feature of the proposed design is the flexibility to enhance the quantum circuit emulation accuracy at the cost of computational resources. The proposed emulation exhibits two principal properties of the quantum computing i.e. parallelism and probabilistic measurement.
In the past decades, field-programmable gate arrays (FPGAs) have demonstrated an interesting physical platform to facilitate quantum information processing, particularly in the emergence of domain-specific hardware accelerators for quantum computing emulation and quantum key distillation. While conventional general-purpose hardware platforms have been used for quantum information processing, FPGAs promise deep pipeline parallelism, adaptable interface, and trivial support for custom-precision operation. Therefore, the time is ripe for describing recent development of quantum computing emulators and quantum key distillation accelerators on FPGAs. In this article, we provide a comprehensive review of the state-of-the-art in this active field, with a balance between theoretical, implementational, and technological results. Challenges and promising research opportunities are also discussed.