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IEEE Conference on Nanotechnology (IEEE NANO)

CMOS Integrated Single Electron Transistor Electrometry (CMOS-SET) Circuit Design for Nanosecond Quantum-Bit Read-out

Thomas M. Gurrieri, Malcolm S. Carroll, Michael P Lilly, James E. Levy

Published Aug 1, 2008• 13 citations
Publisher

Abstract

Novel single electron transistor (SET) read-out circuit designs are described. The circuits use a silicon SET interfaced to a CMOS voltage mode or current mode comparator to obtain a digital read-out of the state of the qubit. The design assumes standard submicron (0.35 um) CMOS SOI technology using room temperature SPICE models. Implications and uncertainties related to the temperature scaling of these models to 100mK operation are discussed. Using this technology, the simulations predict a read-out operation speed of approximately Ins and a power dissipation per cell as low as 2nW for single-shot read-out, which is a significant advantage over currently used radio frequency SET (RF-SET) approaches.

DOI
10.1109/nano.2008.183

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Cryogenic CMOS Integrated Circuits for Scalable Readout of Silicon Quantum Computers

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Quantum computing promises to revolutionize our lives, achieving unprecedented computational powers and unlocking new possibilities in drug discovery, chemical simulations and cryptography. The fundamental unit of computation of a quantum computer is the quantum bit (qubit). It can be implemented in a number of technologies, such as superconducting qubits, spin qubits, photonic systems, trapped ions and NV-centers. Solid-state superconducting qubits and spin qubits seem to be the most promising ones, as shown by the recent demonstration of quantum supremacy with a superconducting qubit processor. Such quantum processors, to operate in the quantum regime, require very low temperatures around 10 mK, and they are hence kept inside dilution fridges. The electronics required to read out and control such processors is typically realized by discrete components or bulky scientific instruments at room temperature wired into the dilution fridge. Such approach is only feasible until few (< 100) qubits are handled, but it is not scalable for million-qubit processors required for fault-tolerant operation. In this thesis, readout and control electronics is proposed to be integrated and operated directly at cryogenic temperatures, in close proximity with the qubits and potentially even co-integrated. CMOS technology is advocated for its scalability, compactness and low prototyping cost, to create a comprehensive cryo-CMOS class of fully-integrated transceivers to read out and control solid-state qubits. In particular, the thesis focuses on cryo-CMOS radio-frequency integrated circuits for the readout of silicon quantum computers, looking to integrate the whole readout system, from the quantum layer to the room temperature user interface. Cryogenic CMOS devices are explored first, to lay the foundations of integrated circuit design. The realization of quantum dots in standard CMOS technology is explored as a platform to realize solid-state qubit arrays, demonstrating functionality at 50 mK and good reproducibility. Moreover, the operation of integrated transistors at 50 mK and 4.2 K is explored to understand their basic cryogenic functionality, through characterization and modeling. Then also integrated passives, such as capacitors, inductors and transformers, are studied and modeled at cryogenic temperatures. Then, a fully-integrated readout platform spanning across all the blocks needed for dispersive readout is proposed. A fully-integrated matrix of quantum dots with radio-frequency gate-based readout capabilities is demonstrated along with time- and frequency-multiplexing. This quantum-classical circuit shows all the features for a scalable approach and is the core of the platform following it. A cryogenic CMOS circulator based on a new all-pass filter architecture is demonstrated, to be used as integrated replacement for current bulky counterparts; it allows power reduction, insertion loss and bandwidth enhancement with respect to state-of-the-art integrated circulators. The rest of the front-end is also explored with dedicated test multiplexers, a low noise-amplifier and an oscillator, that are finally merged in a single fully-integrated low-noise receiver with frequency synthesizer operating at 3.5 K for scalable multiplexed readout of silicon qubits. The platform presented in this thesis, across temperature boundaries, carries all the features required for future scalable silicon quantum computing platforms and could therefore form their core.

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Sithumini Ekanayake, Torsten Lehmann, Andrew S. Dzurak +1 more

Quantum bit (qubit) control and readout requires controller-qubit-observer systems for rapid control signal generation and injection to the qubit gates, and observation of their final state projections. Conventionally, for solid-state qubits, this is achieved by generating the control signal at 300 K and transmitting it along very long coaxial cables that span from 300 K to sub-K (typically les 500 mK), then reading out the response from charge proximity sensors such as single-electron transistors along similar lengths of cable. Our approach is to fabricate the classical controller and observer circuits using a commercial foundry processed silicon-on-sapphire (SOS) RFCMOS technology for operation at low temperatures (either at 4.2 K, 1 K, or sub-K). We have demonstrated SOS-CMOS NFET and PFET device operation at 4.2 K, and sub-K that showed deviations from their 300 K characteristics, but with further experiments these were shown to have minimal effects on control circuit function. Using these results, we have fabricated and demonstrated a low-power proof-of-concept SOS-CMOS controller circuit (monostable 100 ps voltage-pulse generator) that can operate at sub-K temperatures in a dilution refrigerator. We briefly discuss experimental and conceptual schemes with which we can develop qubit control systems for cryogenic and lower temperatures. These low temperature experiments also demonstrate that commercial SOS RF-CMOS technology can be feasible for other low temperature and low power applications.

IEEE Conference on Nanotechnology (IEEE NANO)•Aug 1, 2007•9 citations
Novel single electron transistor (SET) read-out circuit designs are described. The circuits use a silicon SET interfaced to a CMOS voltage mode or current mode comparator to obtain a digital read-out of the state of the qubit. The design assumes standard submicron (0.35 um) CMOS SOI technology using room temperature SPICE models. Implications and uncertainties related to the temperature scaling of these models to 100mK operation are discussed. Using this technology, the simulations predict a read-out operation speed of approximately Ins and a power dissipation per cell as low as 2nW for single-shot read-out, which is a significant advantage over currently used radio frequency SET (RF-SET) approaches.
The Single Electron Transistor holds the potential to be a suitable readout device for future solid-state quantum computers. The low temperature measurement results of a 0.5 μm Silicon-On-Sapphire CMOS circuit designed to interface with a Single Electron Transistor are presented. Careful design of the experimental set-up is critical for conducting the circuit test and performance measurements at cryogenic temperatures. The circuit operates at 4 K and achieves single-shot readout with a resolution in the order of one nanoampere. A detection delay as low as 1.5 μs is recorded while dissipating only 20-30 μW power.
Quantum computing promises to revolutionize our lives, achieving unprecedented computational powers and unlocking new possibilities in drug discovery, chemical simulations and cryptography. The fundamental unit of computation of a quantum computer is the quantum bit (qubit). It can be implemented in a number of technologies, such as superconducting qubits, spin qubits, photonic systems, trapped ions and NV-centers. Solid-state superconducting qubits and spin qubits seem to be the most promising ones, as shown by the recent demonstration of quantum supremacy with a superconducting qubit processor. Such quantum processors, to operate in the quantum regime, require very low temperatures around 10 mK, and they are hence kept inside dilution fridges. The electronics required to read out and control such processors is typically realized by discrete components or bulky scientific instruments at room temperature wired into the dilution fridge. Such approach is only feasible until few (< 100) qubits are handled, but it is not scalable for million-qubit processors required for fault-tolerant operation. In this thesis, readout and control electronics is proposed to be integrated and operated directly at cryogenic temperatures, in close proximity with the qubits and potentially even co-integrated. CMOS technology is advocated for its scalability, compactness and low prototyping cost, to create a comprehensive cryo-CMOS class of fully-integrated transceivers to read out and control solid-state qubits. In particular, the thesis focuses on cryo-CMOS radio-frequency integrated circuits for the readout of silicon quantum computers, looking to integrate the whole readout system, from the quantum layer to the room temperature user interface. Cryogenic CMOS devices are explored first, to lay the foundations of integrated circuit design. The realization of quantum dots in standard CMOS technology is explored as a platform to realize solid-state qubit arrays, demonstrating functionality at 50 mK and good reproducibility. Moreover, the operation of integrated transistors at 50 mK and 4.2 K is explored to understand their basic cryogenic functionality, through characterization and modeling. Then also integrated passives, such as capacitors, inductors and transformers, are studied and modeled at cryogenic temperatures. Then, a fully-integrated readout platform spanning across all the blocks needed for dispersive readout is proposed. A fully-integrated matrix of quantum dots with radio-frequency gate-based readout capabilities is demonstrated along with time- and frequency-multiplexing. This quantum-classical circuit shows all the features for a scalable approach and is the core of the platform following it. A cryogenic CMOS circulator based on a new all-pass filter architecture is demonstrated, to be used as integrated replacement for current bulky counterparts; it allows power reduction, insertion loss and bandwidth enhancement with respect to state-of-the-art integrated circulators. The rest of the front-end is also explored with dedicated test multiplexers, a low noise-amplifier and an oscillator, that are finally merged in a single fully-integrated low-noise receiver with frequency synthesizer operating at 3.5 K for scalable multiplexed readout of silicon qubits. The platform presented in this thesis, across temperature boundaries, carries all the features required for future scalable silicon quantum computing platforms and could therefore form their core.
In the pursuit of quantum computing, solid-state quantum systems, particularly superconducting ones, have made remarkable advancements over the past two decades. However, achieving fault-tolerant quantum computing for next-generation applications necessitates the integration of several million qubits, which presents significant challenges in terms of interconnection complexity and latency that are currently unsolvable with state-of-the-art room-temperature control and readout electronics. Recently, cryogenic integrated circuits (ICs), including CMOS radio-frequency ICs and rapid-single-flux-quantum-logic ICs, have emerged as potential alternatives to room-temperature electronics. Unlike their room-temperature counterparts, these ICs are deployed within cryostats to enhance scalability by reducing the number and length of transmission lines. Additionally, operating at cryogenic temperatures can suppress electronic noise and improve qubit control fidelity. However, for CMOS ICs specifically, circuit design uncertainties arise due to a lack of reliable models for cryogenic field effect transistors as well as issues related to severe fickle noises and power dissipation at cryogenic temperatures. This paper provides a comprehensive review of recent research on both types of cryogenic control and readout ICs but primarily focuses on the more mature CMOS technology. The discussion encompasses principles underlying control and readout techniques employed in cryogenic CMOS ICs along with their architectural designs; characterization and modeling approaches for field effect transistors under cryogenic conditions; as well as fundamental concepts pertaining to rapid single flux quantum circuits.
We describe fabrication and measurements of Single Electron Transistors operated in the Radio Frequency mode (RF-SET). We demonstrate very high sensitivity for RF-SETs and we evaluate the back-action from an RF-SET, when used as a read-out device for charge qubits. We conclude that single-shot read-out is possible with a signal to noise ratio greater than one, and that niobium qubits would substantially improve the signal to noise ratio. Furthermore we describe how the RF-SET could be used to read out a differential qubit in a gradiometer coupling.
A major problem of usual current measurement setup is the severe limitations on the bandwidth due to room temperature electronics. This restricts the practical measurement rate to below 10 Hz and makes impossible to observe the evolution of a quantum state in real time. Here we describe a measurement on a silicon single electron transistor (SET) carried out using a custom CMOS measurement circuit in close proximity to the device under test. Both the device and the CMOS circuit are maintained in the same cryogenic environment. Quantum mechanical states in the single electron transistor (SET) were mapped by continuous microwave spectroscopy. The real time evolution of a particularly long lived quantum mechanical state was observed in a single shot measurement, made possible by the much faster measurement rate. This technique will shortly be applied to the measurement of coherent states in a charge qubit device made of a silicon double dot.
Quantum bit (qubit) control and readout requires controller-qubit-observer systems for rapid control signal generation and injection to the qubit gates, and observation of their final state projections. Conventionally, for solid-state qubits, this is achieved by generating the control signal at 300 K and transmitting it along very long coaxial cables that span from 300 K to sub-K (typically les 500 mK), then reading out the response from charge proximity sensors such as single-electron transistors along similar lengths of cable. Our approach is to fabricate the classical controller and observer circuits using a commercial foundry processed silicon-on-sapphire (SOS) RFCMOS technology for operation at low temperatures (either at 4.2 K, 1 K, or sub-K). We have demonstrated SOS-CMOS NFET and PFET device operation at 4.2 K, and sub-K that showed deviations from their 300 K characteristics, but with further experiments these were shown to have minimal effects on control circuit function. Using these results, we have fabricated and demonstrated a low-power proof-of-concept SOS-CMOS controller circuit (monostable 100 ps voltage-pulse generator) that can operate at sub-K temperatures in a dilution refrigerator. We briefly discuss experimental and conceptual schemes with which we can develop qubit control systems for cryogenic and lower temperatures. These low temperature experiments also demonstrate that commercial SOS RF-CMOS technology can be feasible for other low temperature and low power applications.