Quantum bit (qubit) control and readout requires controller-qubit-observer systems for rapid control signal generation and injection to the qubit gates, and observation of their final state projections. Conventionally, for solid-state qubits, this is achieved by generating the control signal at 300 K and transmitting it along very long coaxial cables that span from 300 K to sub-K (typically les 500 mK), then reading out the response from charge proximity sensors such as single-electron transistors along similar lengths of cable. Our approach is to fabricate the classical controller and observer circuits using a commercial foundry processed silicon-on-sapphire (SOS) RFCMOS technology for operation at low temperatures (either at 4.2 K, 1 K, or sub-K). We have demonstrated SOS-CMOS NFET and PFET device operation at 4.2 K, and sub-K that showed deviations from their 300 K characteristics, but with further experiments these were shown to have minimal effects on control circuit function. Using these results, we have fabricated and demonstrated a low-power proof-of-concept SOS-CMOS controller circuit (monostable 100 ps voltage-pulse generator) that can operate at sub-K temperatures in a dilution refrigerator. We briefly discuss experimental and conceptual schemes with which we can develop qubit control systems for cryogenic and lower temperatures. These low temperature experiments also demonstrate that commercial SOS RF-CMOS technology can be feasible for other low temperature and low power applications.
Quantum bit (qubit) control and readout requires controller-qubit-observer systems for rapid control signal generation and injection to the qubit gates, and observation of their final state projections. Conventionally, for solid-state qubits, this is achieved by generating the control signal at 300 K and transmitting it along very long coaxial cables that span from 300 K to sub-K (typically les 500 mK), then reading out the response from charge proximity sensors such as single-electron transistors along similar lengths of cable. Our approach is to fabricate the classical controller and observer circuits using a commercial foundry processed silicon-on-sapphire (SOS) RFCMOS technology for operation at low temperatures (either at 4.2 K, 1 K, or sub-K). We have demonstrated SOS-CMOS NFET and PFET device operation at 4.2 K, and sub-K that showed deviations from their 300 K characteristics, but with further experiments these were shown to have minimal effects on control circuit function. Using these results, we have fabricated and demonstrated a low-power proof-of-concept SOS-CMOS controller circuit (monostable 100 ps voltage-pulse generator) that can operate at sub-K temperatures in a dilution refrigerator. We briefly discuss experimental and conceptual schemes with which we can develop qubit control systems for cryogenic and lower temperatures. These low temperature experiments also demonstrate that commercial SOS RF-CMOS technology can be feasible for other low temperature and low power applications.
Solid-state quantum bits (qubits) generally require cryogenic operating temperatures together with rapid voltage (or current) pulse generation for qubit control and readout. Conventionally this is achieved by generating the signals at 300 K, transmitting them along very long coaxial cables that span ges 4 m from 300 K to sub-K (30-500 mK) into a dilution refrigerator, and reading-out the final qubit states via similar lengths of cable. Here we fabricate the control-pulse generator circuits using a foundry-processed SOS-CMOS technology that is capable of operation down to sub-K temperatures so that control signals can be generated at cryogenic temperatures in the near vicinity of the qubits. We present two full-custom large-scale integrated (LSI) control-pulse generator circuits: (a) a mixed-mode; and (b) a digital design each comprising hundreds of devices, and show pulse characteristics at 4.2 K, demonstrating LSI circuit operation at low temperatures. The mixed-mode design showed lower power dissipation but had increasing jitter at longer dwell times. The digital design eliminated jitter but at the expense of increased power dissipation. Although power dissipation is higher in the digital design, it should be possible to thermally anchor such control circuits at the 1 K stage of a dilution refrigerator thereby minimizing heat propagation to the qubits.
Quantum computing promises to revolutionize our lives, achieving unprecedented computational powers and unlocking new possibilities in drug discovery, chemical simulations and cryptography. The fundamental unit of computation of a quantum computer is the quantum bit (qubit). It can be implemented in a number of technologies, such as superconducting qubits, spin qubits, photonic systems, trapped ions and NV-centers. Solid-state superconducting qubits and spin qubits seem to be the most promising ones, as shown by the recent demonstration of quantum supremacy with a superconducting qubit processor. Such quantum processors, to operate in the quantum regime, require very low temperatures around 10 mK, and they are hence kept inside dilution fridges. The electronics required to read out and control such processors is typically realized by discrete components or bulky scientific instruments at room temperature wired into the dilution fridge. Such approach is only feasible until few (< 100) qubits are handled, but it is not scalable for million-qubit processors required for fault-tolerant operation. In this thesis, readout and control electronics is proposed to be integrated and operated directly at cryogenic temperatures, in close proximity with the qubits and potentially even co-integrated. CMOS technology is advocated for its scalability, compactness and low prototyping cost, to create a comprehensive cryo-CMOS class of fully-integrated transceivers to read out and control solid-state qubits. In particular, the thesis focuses on cryo-CMOS radio-frequency integrated circuits for the readout of silicon quantum computers, looking to integrate the whole readout system, from the quantum layer to the room temperature user interface. Cryogenic CMOS devices are explored first, to lay the foundations of integrated circuit design. The realization of quantum dots in standard CMOS technology is explored as a platform to realize solid-state qubit arrays, demonstrating functionality at 50 mK and good reproducibility. Moreover, the operation of integrated transistors at 50 mK and 4.2 K is explored to understand their basic cryogenic functionality, through characterization and modeling. Then also integrated passives, such as capacitors, inductors and transformers, are studied and modeled at cryogenic temperatures. Then, a fully-integrated readout platform spanning across all the blocks needed for dispersive readout is proposed. A fully-integrated matrix of quantum dots with radio-frequency gate-based readout capabilities is demonstrated along with time- and frequency-multiplexing. This quantum-classical circuit shows all the features for a scalable approach and is the core of the platform following it. A cryogenic CMOS circulator based on a new all-pass filter architecture is demonstrated, to be used as integrated replacement for current bulky counterparts; it allows power reduction, insertion loss and bandwidth enhancement with respect to state-of-the-art integrated circulators. The rest of the front-end is also explored with dedicated test multiplexers, a low noise-amplifier and an oscillator, that are finally merged in a single fully-integrated low-noise receiver with frequency synthesizer operating at 3.5 K for scalable multiplexed readout of silicon qubits. The platform presented in this thesis, across temperature boundaries, carries all the features required for future scalable silicon quantum computing platforms and could therefore form their core.
A fault tolerant scalable quantum computer requires more than 1000 Qubits to perform real time state correction and to improve the Qubit coherence time. The dense wiring connections required between the quantum processor placed at a 100 mK temperature and the room temperature control and readout electronics serve as a limiting factor in this system. Qubit control and readout electronics operating at 4 K temperature, placed closer to a quantum processor inside the dilution refrigerator avoids the dense wiring connections to room temperature electronics, and hence, serve as a potential solution to realize a scalable quantum computer. However, with no CMOS process technology models available at cryogenic temperatures, the design of a fully integrated, ultra-low power Qubit control and readout electronics at a sub-1 mW power consumption proves to be extremely challenging. In recent years, there has been a huge rise in interest among the research communities to understand and solve the device and circuit level challenges at deep cryogenic temperatures. This paper presents an overview of the recently published active and passive device nonidealities, circuit design challenges and solutions, and the future research directions in the Qubit control and readout electronics operating at deep cryogenic temperatures.
Quantum computing promises an exponential speed-up of computation compared to what is nowadays achievable with classical computers. In this way, it enables the evaluation of more complex models and the breaching of current security algorithms. For the operation of a quantum system, many questions remain to be answered. Currently, there are several quantum technologies that promise to be both reliable and scalable, two features required for large scale quantum operations. Common to all technologies is the operating temperature that needs to be close to absolute zero, i.e. below 100 mK, to suppress environment noise and allow the quantum properties to become 'visible'. In order for any quantum processor to be operated, a so-called quantum-classical interface is required for the quantum bit (qubit) read-out and control. This interface consists of various electronic blocks, such as analog-to-digital converters, digital-to-analog converters, mixers, amplifiers and a digital controller. Especially the analog blocks require effort to meet the noise and stability constraints as not to disturb the very sensitive qubits and allow reading of the tiny signals. As the qubits live in extremely deep-cryogenic temperatures, long wires interface the cryogenic with the room temperature environment, where most of the electronics is situated. However, for a scalable system, heat injection becomes a serious problem, with many wires between 300 K and sub-Kelvin. Furthermore, such amount of interconnects is challenging to mechanically place in a dilution refrigerator. Therefore, in this work, we propose to implement the electronics not at room temperature, but at a temperature much closer to the qubits, for example at 4 K. This not only reduces significantly the wiring between room temperature and the qubits, but we can also benefit from lower electronic noise at such a temperature. The operation of conventional electronics almost 200°C below its normal temperature range is not trivial as device properties alter significantly and most circuits no longer operate as intended. In CMOS processes, the main technology in the integrated electronics world, the behaviour of the transistors, required for the implementation of any circuit, deviates considerably at low temperatures. The transistor's threshold voltage goes up, the mobility increases and the subthreshold slope becomes steeper, to name just a few of these deviations. Although there are improvements in performance, there are also some counter effects, and characterization of the transistors is needed to observe the changes. Once devices are characterized at such low temperatures, new models can be built and circuits can be simulated and adapted to operate properly at cryogenic temperatures. Luckily, there are various commercially available devices that can already withstand the chills of cold. We demonstrated various commercially available devices, such as a field-programmable gate array (FPGA) implemented in a 28 nm CMOS process, to be operating without major concerns at 4~K. Its properties alter only slightly, within 5 to 10%, and all tested circuit implementations, working at 300~K, also worked at 4 K. We combined both commercially available devices, that operate 200 K below their specified temperature range, with custom designed CMOS circuits to implement a cryogenic read-out platform for spin qubits. This system comprises amplifiers, an ADC, an FPGA, voltage regulators and a clock generator. It allows to amplify the tiny signal from the qubits and digitize it directly in the FPGA in order to process the data locally at 4~K. This system is one of the first systematic attempts at operating a part of the quantum-classical interface at cryogenic temperatures and forms the basis for future systems comprising the complete electronic interface for qubits to operate at such low temperatures. One of the main problems to tackle for cryogenic electronic systems is their power consumption. Power budgets are simply limited to roughly 1 or 2 Watts at 4 K and exponentially lower at deeper cryogenic temperatures, thus limiting the size of large-scale electronic systems. Our approach of combined commercial and custom circuits will have to be steadily replaced by a single (custom) technology that meets both power and scalability constraints. One of the best candidates is CMOS, a technology that the industry has relied upon for several decades and benefits from many optimizations thanks to Moore's law.
A scaled-up quantum computer will require a highly efficient control interface that autonomously manipulates and reads out large numbers of qubits, which for solid-state implementations are usually held at millikelvin (mK) temperatures. Advanced CMOS technology, tightly integrated with the quantum system, would be ideal for implementing such a control interface but is generally discounted on the basis of its power dissipation that leads to heating of the fragile qubits. Here, we demonstrate an ultra low power, CMOS-based quantum control platform that takes digital commands as input and generates many parallel qubit control signals. Realized using 100,000 transistors operating near 100 mK, our platform alleviates the need for separate control lines to every qubit by exploiting the low leakage of transistors at cryogenic temperatures to store charge on floating gate structures that are used to tune-up quantum devices. This charge can then be rapidly shuffled between on-chip capacitors to generate the fast voltage pulses required for dynamic qubit control. We benchmark this architecture on a quantum dot test device, showing that the control of thousands of gate electrodes is feasible within the cooling power of commercially available dilution refrigerators.
Cryogenic CMOS control and readout circuits tightly interfaced with the qubits have emerged as a promising solution for future quantum computers with tens-of-thousands to millions of qubits [1] –[5]. A lownoise cryo-CMOS receiver at 3−4K integrated tightly with the lowcryogenic quantum processor can relax or even potentially eliminated the need for the HEMT LNA, and keep the whole control loop at cryogenic temperature, hence avoiding any high-speed interconnects to room temperature (Fig. 1). Additionally, wide bandwidths in the receiver enables qubit-multiplexing, where qubits can be frequency multiplexed with a spacing of 10MHz−40MHz, allowing anywhere from 10’s-100’s of qubits to be packed in to a single readout line with gigahertz-scale bandwidths. A second critical metric is power consumption, since the cooling power available in a typical dilution refrigerator is limited to a few watts at 3−4K. Therefore, the control and readout circuits should be designed with low power consumption, projected to be <1mW per qubit (Fig. 1). While there has been initial progress in the design of cryo-CMOS readout systems, a leap forward is required in their overall power consumption to be viable for future quantum systems. In this work, we showcase the design and implementation of the first sub-mWper-qubit cryo-CMOS RX - a wideband, I/Q-downconversion, 4K receiver for qubit readout that achieves >1.9GHz of IF bandwidth with >50dB conversion gain and 0.7dB NF while consuming only 17mW of power consumption, thanks to various design techniques including near-threshold operation and low-1/f-noise passive mixers, representing 3−5× lower power consumption than prior works [2]–[3] while achieving similar noise, BW and gain performance. In addition, we demonstrate a real-time qubit read-out measurement by integrating our cryogenic-CMOS receiver with a transmon qubit.