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IEEE Transactions on Applied Superconductivity

Can RSFQ logic circuits be scaled to deep submicron junctions?

Alan M. Kadin, C.A. Mancini, M. J. Feldman, DARREN K. BROCK

Published Mar 1, 2001• 40 citations
Publisher

Abstract

Scaling of niobium RSFQ integrated circuit technology to deep submicron dimensions (linewidths of 300 nm or less) should permit increased clock rate (up to 250 GHz) and increased areal density of Josephson junctions (up to 1 million junctions/cm/sup 2/), without the need for external shunt resistors. It is shown how existing circuit layouts can be scaled down to these dimensions, while maintaining the precise timing essential for correct operation. Additional issues related to the practical realization of such circuits are discussed, including effects of self-heating and models for the generation and propagation of sub-ps single-flux-quantum pulses.

DOI
10.1109/77.919528

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Scaling of niobium RSFQ integrated circuit technology to deep submicron dimensions (linewidths of 300 nm or less) should permit increased clock rate (up to 250 GHz) and increased areal density of Josephson junctions (up to 1 million junctions/cm/sup 2/), without the need for external shunt resistors. It is shown how existing circuit layouts can be scaled down to these dimensions, while maintaining the precise timing essential for correct operation. Additional issues related to the practical realization of such circuits are discussed, including effects of self-heating and models for the generation and propagation of sub-ps single-flux-quantum pulses.
Abstract We review the existing fabrication processes for superconductor digital electronics and describe approaches to increasing the scale of integration of superconducting digital circuits from the current level of about one million Josephson junctions (JJs) on a 1-cm 2 chip toward ten million JJs per chip. We present designs of ac-clocked Single Flux Quantum (SFQ) shift registers, convenient benchmarking circuits, in a 250-nm-linewidth superconductor electronics fabrication process developed recently at MIT Lincoln Laboratory (MIT LL). For shift registers using resistively shunted JJs with Josephson critical current density, J c of 100 μA/μm 2 , we achieved a record-high circuit density of 4.2·10 6 JJs per cm 2 , a factor of three higher than the previous record obtained in the MIT LL 350-nm-linewidth SFQ5ee process. Using self-shunted JJs with J c of 600 μA/μm 2 , we increased this record circuit density to 7.4·10 6 JJs per cm 2 .
Superconducting circuits based upon Rapid Single Flux Quantum (RSFQ) Logic are an interesting approach for future digital electronics with clock frequencies in the range of 100 GHz. Our intention is to increase the integration density of such circuits. Therefore we have successfully fabricated and tested an RSFQ-circuit based on a new kind of stacked three terminal device, henceforth called a "stacktron". A stacktron consists of two vertically arranged all-niobium tunnel junctions, each separately shunted by a thin film resistor, and an access to the intermediate niobium layer. An RSFQ frequency divider (T-flip-flop) including two stacktrons has been tested up to 20 GHz. As a shunt resistor we used Pd/Au, so that /spl beta//sub c/<1 and the IV-curve is nonhysteretic. The junctions showed a current density of approximately 250 A/cm/sup 2/. The I/sub c/R/sub n/-product was 100 /spl mu/V. These first steps toward a three dimensional (3D) RSFQ architecture will be discussed in the framework of highly integrated and complex RSFQ-circuits.
Recent developments concerning the rapid single-flux-quantum (RSFQ) circuit family are reviewed. Elementary cells in this circuit family can generate, pass, memorize, and reproduce picosecond voltage pulses with a nominally quantized area corresponding to transfer of a single magnetic flux quantum across a Josephson junction. Functionally, each cell can be viewed as a combination of a logic gate and an output latch (register) controlled by clock pulses, which are physically similar to the signal pulses. Hand-shaking style of local exchange by the clock pulses enables one to increase complexity of the LSI RSFQ systems without loss of operating speed. The simplest components of the RSFQ circuitry have been experimentally tested at clock frequencies exceeding 100 GHz, and an increase of the speed beyond 300 GHz is expected as a result of using an up-to-date fabrication technology. This review includes a discussion of possible future developments and applications of this novel, ultrafast digital technology.>
Superconductive Rapid Single Flux Quantum (RSFQ) logic and memory, in which ones and zeros are represented by the presence or absence within a timing window of quantized picosecond voltage pulse (/spl int/v(t)dt=h/2e=2.07 mV/spl middot/ps), corresponding to one SFQ, can be integrated into a digital computing system with an operating rate of several tens of GHz, based on the present Nb Josephson junction integrated circuit technology. It is the most promising technology beyond semiconductor transistors for low-power high-end computation. However, as the operating speed of circuits and systems increase, timing uncertainty from fabrication process variations makes global synchronization very hard. In this paper, we present a globally asynchronous, locally synchronous timing methodology for RSFQ digital design, which can solve the global synchronization problem. We also demonstrate the recent experimental results of some asynchronous circuits and systems implemented in RSFQ technology. Several key components such as a self-timed shift register, a self-timed demultiplexor, a Muller-C element, a completion detector, and a clock generator have been designed and tested. High speed operation has been confirmed up to 20 Gb/s for a prototype data buffer system, which consists two self-timed shift registers and an on-chip 5-38 GHz clock generator.
A simple test circuit of the rapid single-flux-quantum (RSFQ) logic family has been implemented in a planarized all-refractory technology using only two superconducting layers and small Nb/AlOx/Nb Josephson junctions (nominally 1.5×1.5 μm2) with critical current density jc≊6 kA/cm2. A special layout design of the integrated circuit (including a SFQ pulse generator, Josephson transmission line, and T flip–flop) was used to reduce 3D inductances resulting from absence of the ground plane. For samples with various junction parameters, the maximum frequency of the SFQ pulse train, which could be divided by 2 by the flip–flop, ranged from 200 to 370 GHz.
Superconducting digital circuits based on Josephson junctions with amorphous niobium-silicon (a-NbSi) barriers have been designed, fabricated, and tested. Single-flux-quantum (SFQ) shift registers operated with ±30% bias margins, confirming junction reproducibility and uniformity. Static digital dividers operated up to 165 GHz for a single value of bias current, which was only marginally slower than circuits fabricated with externally shunted AlOx-barrier junctions having a comparable critical current density of 4.5 kA/cm2. In comparison, self-shunted a-NbSi junctions enabled a doubling in circuit density. This and their relatively thick 10 nm barriers could increase the yield of complex SFQ circuits.