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IEEE Transactions on Applied Superconductivity

Margins and yield in single flux quantum logic

C.A. Hamilton, K.C. Gilbert

Published Jan 1, 1991• 76 citations
Publisher

Abstract

Simulations are used to optimize the design of simple rapid single flux quantum (RSFQ) logic gates and to determine their margins. Optimizations based on maximizing the smallest (critical) margin result in critical margins in the range of 19-50%. A Monte Carlo approach is used to illustrate the relationship between margins and process yield. Based on single gate simulations, the results show that 1 sigma parameter spreads of less than about +or-5% will be required to make medium- or large-scale integrated RSFQ logic circuits. A single-bit full adder using five RSFQ gates and a local self-timing network are simulated with discrete components. The full adder used 2000-A/cm/sup 2/ junctions with a specific capacitance of 0.04 pF/ mu /sup 2/ and had a logic delay of 87 ps and a worst-case margin of +or-19%. A small margin reduction which is not present in the individual gate simulations results from loading.>

DOI
10.1109/77.107400

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Simulations are used to optimize the design of simple rapid single flux quantum (RSFQ) logic gates and to determine their margins. Optimizations based on maximizing the smallest (critical) margin result in critical margins in the range of 19-50%. A Monte Carlo approach is used to illustrate the relationship between margins and process yield. Based on single gate simulations, the results show that 1 sigma parameter spreads of less than about +or-5% will be required to make medium- or large-scale integrated RSFQ logic circuits. A single-bit full adder using five RSFQ gates and a local self-timing network are simulated with discrete components. The full adder used 2000-A/cm/sup 2/ junctions with a specific capacitance of 0.04 pF/ mu /sup 2/ and had a logic delay of 87 ps and a worst-case margin of +or-19%. A small margin reduction which is not present in the individual gate simulations results from loading.>
The authors consider the design of a binary carry full-adder cell using the logic gates and buffers belonging to the rapid single-flux-quantum (RSFQ) logic family. They have taken advantage of the unique properties of RSFQ pulse logic to realize two designs: one using two logic gates and a toggle flip-flop in two stages of logic, the other using two logic gates in one stage of logic. They have determined the parameter margins of the two full-adder cells and optimized them to obtain critical margins approaching +or-30%. Simulations of the full-adder cells have revealed critical delays and maximum clock frequencies of 58 ps and 17 GHz and 33 ps and 30 GHz, respectively.>
Among the major issues in modern large-scale rapid single-flux quantum (RSFQ) circuits are the complexity of the clock network, tight timing tolerances, poor applicability of existing CMOS-based design algorithms, and extremely deep pipelines, which reduce the effective clock frequency. In this article, asynchronous dynamic single-flux quantum majority gates are proposed to solve some of these problems. The proposed logic gates exhibit high bias margins and do not require significant area or a large number of Josephson junctions as compared to existing RSFQ logic gates. These gates exhibit a tradeoff among the input skew tolerance, clock frequency, and bias margins. Asynchronous logic gates greatly reduce the complexity of the clock network in large-scale RSFQ circuits, thereby alleviating certain timing issues and reducing the required bias currents. Furthermore, asynchronous logic allows existing design algorithms to utilize CMOS approaches for synthesis, verification, and testability. The adoption of majority logic in complex RSFQ circuits also reduces the pipeline depth, enabling higher clock speeds in very large scale integration RSFQ circuits.
Rapid single flux quantum (RSFQ) logic is a digital circuit technology that in recent years has presented itself as an alternative to semiconductors in the application of ultra high speed, very low power applications. The optimal timing of digital circuits operating at hundreds of GHz is still a complex problem for both RSFQ and semiconductor technologies. The fact that most RSFQ gates require a clock signal to function makes this even more complex. Various RSFQ timing schemes have been adapted from semiconductor design methodologies, and some have been designed specifically for RSFQ. Currently, synchronous clocking schemes outperform other schemes, but with the scale of RSFQ circuits ever increasing, the proper use of timing schemes are becoming more crucial. This paper describes a new asynchronous self-timing scheme where the details of clock distribution and clocking are built into the logic gates. Tests were done on the newly developed asynchronous logic gates and an asynchronous full adder was implemented and tested
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Rapid Single Flux Quantum (RSFQ) circuits must be designed with large operating margins because of variations in the fabrication process. We describe a routine to optimize the yield, rather than the critical margin, of RSFQ circuits, based on the method of inscribed hyperspheres. The operating region is mapped out with a minimum of circuit simulations taking into account the relative size of the process variations. The method is effective for as many as nine parameters. We show that the standard optimization of critical margin will often give a seriously wrong result for multidimensional parameter space.>
We present a new design technique of rapid single-flux-quantum (RSFQ) logic gates for low-noise, high-speed operation. In this study, we propose the use of a damping resistor shared with a junction pair composing a comparator, in addition to their individual shunt resistors increased from the standard values. We analyzed timing characteristics and bit error rates (BERs) of several RSFQ flip-flops composed of the proposed comparators using numerical simulation. The proposed comparator showed reduced timing jitter by ~5% in association with small delay time, sharpened BER curves, and improvement in operating margins by 2-3% compared to the standard design. We fabricated 2-bit shift registers using the noise reduction technique. We obtained sharp BER curves from the measurement. The proposed method indicated that it gave wide margins.