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IEICE Transactions on Communications

Lowering Error Floors of Irregular LDPC Codes by Combining Construction and Decoding

Xiaopeng Jiao, Jianjun Mu, Fan FANG, Rong Xia Sun

Published Jan 1, 2012• 1 citation
Publisher

Abstract

Irregular low-density parity-check (LDPC) codes generally have good decoding performance in the waterfall region, but they exhibit higher error floors than regular ones. In this letter, we present a hybrid method, which combines code construction and the iterative decoding algorithm, to tackle this problem. Simulation results show that the proposed scheme decreases the error floor significantly for irregular LDPC codes over binary-input additive white Gaussian noise (BIAWGN) channel.

DOI
10.1587/transcom.e95.b.271

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•Jan 1, 2005•1 citation
Irregular low-density parity-check (LDPC) codes generally have good decoding performance in the waterfall region, but they exhibit higher error floors than regular ones. In this letter, we present a hybrid method, which combines code construction and the iterative decoding algorithm, to tackle this problem. Simulation results show that the proposed scheme decreases the error floor significantly for irregular LDPC codes over binary-input additive white Gaussian noise (BIAWGN) channel.
Irregular Low-Density Parity-Check (LDPC) codes generally achieve better performance than regular LDPC codes at low E b /N 0 values. They have, however, higher error floors than regular LDPC codes. With respect to the construction of the irregular LDPC code, it can achieve the trade-off between the performance degradation of low E b /N 0 region and lowering error floor. It is known that a decoding algorithm can achieve very good performance if it combines the Ordered Statistic Decoding (OSD) algorithm and the Log Likelihood Ratio-Belief Propagation (LLR-BP) decoding algorithm. Unfortunately, all the codewords obtained by the OSD algorithm satisfy the parity check equation of the LDPC code. While we can not use the parity check equation of the LDPC code to stop the decoding process, the wrong codeword that satisfies the parity check equation raises the error floor. Once a codeword that satisfies the parity check equation is generated by the LLR-BP decoding algorithm, we regard that codeword as the final estimate and halt decoding; the OSD algorithm is not performed. In this paper, we propose a new encoding/decoding scheme to lower the error floor created by irregular LDPC codes. The proposed encoding scheme encodes information bits by Cyclic Redundancy Check (CRC) and LDPC code. The proposed decoding scheme, which consists of the LLR-BP decoding, CRC check, and OSD decoding, detects errors in the codewords obtained by the LLR-BP decoding algorithm and the OSD decoding algorithm using the parity check equations of LDPC codes and CRC. Computer simulations show that the proposed encoding/decoding scheme can lower the error floor of irregular LDPC codes.
We propose a technique to design finite-length irregular low-density parity-check (LDPC) codes over the binary-input additive white Gaussian noise (AWGN) channel with good performance in both the waterfall and the error floor region. The design process starts from a protograph which embodies a desirable degree distribution. This protograph is then lifted cyclically to a certain block length of interest. The lift is designed carefully to satisfy a certain approximate cycle extrinsic message degree (ACE) spectrum. The target ACE spectrum is one with extremal properties, implying a good error floor performance for the designed code. The proposed construction results in quasi-cyclic codes which are attractive in practice due to simple encoder and decoder implementation. Simulation results are provided to demonstrate the effectiveness of the proposed construction in comparison with similar existing constructions.
In this paper, a novel methodology for designing structured generalized low-density parity-check (G-LDPC) codes is presented. The proposed design results in quasi-cyclic G-LDPC codes for which efficient encoding is feasible through shift-register-based circuits. The structure imposed on the bipartite graphs, together with the choice of simple component codes, leads to a class of codes suitable for fast iterative decoding. A pragmatic approach to the construction of G-LDPC codes is proposed. The approach is based on the substitution of check nodes in the protograph of a low-density parity-check code with stronger nodes based, for instance, on Hamming codes. Such a design approach, which we call low-density parity-check (LDPC) code doping, leads to low-rate quasi-cyclic G-LDPC codes with excellent performance in both the error floor and waterfall regions on the additive white Gaussian noise channel.
There exist many different algorithms to construct good low-density parity-check (LDPC) codes. To maximize the girth of the bipartite graph, which represents the LDPC code, the progressive edge-growth (PEG) algorithm was introduced. This construction methods leads for irregular LDPC codes to a lower error floor, but also to a performance loss in the waterfall region compared with randomly constructed LDPC codes. In this paper, we describe a modification of the PEG algorithm that improves the performance in the waterfall region. Furthermore, this modified PEG algorithm yields codes with lower error floors and a slightly better performance in the waterfall region than randomly constructed LDPC codes
Abstract: Small stopping sets have been proved to be harmful to the error floor performance of a finite-length irregular low-density parity-check (LDPC) code over the binary erasure channel (BEC). On the additive white gaussian noise (AWGN) channel, small stopping sets are expected to have a similar effect. This paper proposes an algorithm that iteratively removes the small-stopping-set-inducing patterns from the graph of a randomly generated irregular LDPC code by means of node exchange, aiming at enlarging the average size of stopping sets in this code. Computer simulation results show that the short-length LDPC codes after our processing achieve a considerable performance improvement in the low-BER region compared to the randomly generated codes. Key words: Error floor, irregular LDPC codes, iterative processing, small stopping set 1