Large-scale computing system characteristics vary by application class, but power and energy use has become a major problem for all classes. Superconducting computing may be able to serve the needs of these systems significantly better than conventional technology. Recent developments in single flux quantum circuit technology for digital logic include variants with greatly improved energy efficiency. Concepts were investigated for computing systems capable of performance in the range from 1 to 1000 PFLOP/s. The concept systems were constrained to use existing commercial cryogenic refrigerators and Nb superconducting technology. In order to meet the performance goals, cache and main memory capable of operating at cryogenic temperatures will be required. Superconducting computing is shown to be potentially competitive on the basis of power and energy efficiency if key component technologies can meet specific goals. Potential advantages of superconducting computing are identified as well as areas requiring further development.
Large-scale computing system characteristics vary by application class, but power and energy use has become a major problem for all classes. Superconducting computing may be able to serve the needs of these systems significantly better than conventional technology. Recent developments in single flux quantum circuit technology for digital logic include variants with greatly improved energy efficiency. Concepts were investigated for computing systems capable of performance in the range from 1 to 1000 PFLOP/s. The concept systems were constrained to use existing commercial cryogenic refrigerators and Nb superconducting technology. In order to meet the performance goals, cache and main memory capable of operating at cryogenic temperatures will be required. Superconducting computing is shown to be potentially competitive on the basis of power and energy efficiency if key component technologies can meet specific goals. Potential advantages of superconducting computing are identified as well as areas requiring further development.
Summary form only given. Superconducting computing has recently emerged as a potential solution for energy-efficient, large-scale computing. Problems in large-scale computing are reviewed. Superconducting computing is significantly different from conventional technologies and required a feasibility study [1] to evaluate its potential. Concepts were investigated for computing systems capable of performance in the range from 1 to 1000 PFLOP/s. The concept systems were constrained to use existing commercial cryogenic refrigerators and Nb superconducting technology. Superconducting computing was shown to be potentially competitive on the basis of power and energy efficiency if key component technologies can meet specific goals. Challenges for superconducting computing are reviewed. One challenge is that saving significant energy requires large-scale systems due to the requirement for cryogenic refrigeration, but superconducting computing is a technology in its infancy. For example, in 2010 there were a very few foundries for superconducting electronic circuits and only one with very limited access was processing 200 mm wafers. There were also few superconducting digital circuit designers and the electronic design automation (EDA) toolchain could only support development of circuits with a few thousand elements. These challenges are shared with several other alternative technologies being developed for energy-efficient computing. The IARPA Cryogenic Computing Complexity (C3) program is in the process of developing superconducting computing technologies for large-scale applications.
Figures of merit connecting processing capabilities with power dissipated (OpS/Watt, Joule/bit, etc.) are becoming dominant factors in choosing technologies for implementing the next generation of computing and communication network systems. Superconductivity is viewed as a technology capable of achieving higher energy efficiencies than other technologies. Static power dissipation of standard RSFQ logic, associated with dc bias resistors, is responsible for most of the circuit power dissipation. In this paper, we review and compare different superconductor digital technology approaches and logic families addressing this problem. We present a novel energy-efficient single flux quantum logic family, ERSFQ/eSFQ. We also discuss energy-efficient approaches for output data interface and overall cryosystem design.
The last several decades have seen an explosion in the use and size of computers for scientific applications. The US Department of Energy has set an ExaScale computing goal for high performance computing that is projected to be unattainable by current CMOS computing designs [1]. This has led to a renewed interest in superconducting computing as a means of beating these projections. One of the primary requirements of this thrust is the development of an efficient cryogenic memory. Estimates of power consumption of early Rapid Single Flux Quantum (RSFQ) memory designs are on the order of MW, far too steep for any real application [1]. Therefore, other memory concepts are required. S/F/S Josephson Junctions, a class of device in which two superconductors (S) are separated by one or more ferromagnetic layers (F) has shown promise as a memory element. Several different systems have been proposed utilizing either the spin-singlet or spin-triplet superconducting states [2]. This talk will discuss the concepts underpinning these devices, and the recent work done to demonstrate their feasibility. [1] Energy-Efficient Superconducting Computing Power Budgets and Requirements, D. Scott Holmes, Andrew L. Ripple, Marc A. Manheimer, IEEE Trans. Appl. Supercon., Vol 23, No. 3, June 2013 [2] B. M. Niedzielski et al., “Use of Pd-Fe and Ni-Fe-Nb as soft magnetic layers in ferromagnetic Josephson junctions for nonvolatile cryogenic memory,” IEEE Trans. Appl. Supercond., vol. 24, no. 4, Aug. 2014, Art. ID. 1800307.
This paper describes our programme to develop and demonstrate ultra-high performance single flux quantum (SFQ) VLSI technology that will enable superconducting digital processors for petaFLOPS-scale computing. In the hybrid technology, multi-threaded architecture, the computational engine to power a petaFLOPS machine at affordable power will consist of 4096 SFQ multi-chip processors, with 50 to 100 GHz clock frequency and associated cryogenic RAM. We present the superconducting technology requirements, progress to date and our plan to meet these requirements. We improved SFQ Nb VLSI by two generations, to a 8 kA cm −2 , 1.25 µm junction process, incorporated new CAD tools into our methodology, demonstrated methods for recycling the bias current and data communication at speeds up to 60 Gb s −1 , both on and between chips through passive transmission lines. FLUX-1 is the most ambitious project implemented in SFQ technology to date, a prototype general-purpose 8 bit microprocessor chip. We are testing the FLUX-1 chip (5K gates, 20 GHz clock) and designing a 32 bit floating-point SFQ multiplier with vector-register memory. We report correct operation of the complete stripline-connected gate library with large bias margins, as well as several larger functional units used in FLUX-1. The next stage will be an SFQ multi-processor machine. Important challenges include further reducing chip supply current and on-chip power dissipation, developing at least 64 kbit, sub-nanosecond cryogenic RAM chips, developing thermally and electrically efficient high data rate cryogenic-to-ambient input/output technology and improving Nb VLSI to increase gate density.
Quantum computers are emerging as a promising new technology due to their ability to solve complex problems that exceed the capabilities of classical systems in terms of time. Among various implementations, superconducting qubits have become the leading technology due to their scalability and compatibility with quantum error correction mechanisms. Although time has traditionally been the primary focus, energetic efficiency is becoming an increasingly important consideration, especially with the possibility of a quantum energetic advantage. In this article, the energy consumption of the Semiclassical Quantum Fourier Transform was analyzed on a superconducting quantum computing platform based on cat qubits. Quantum error correction mechanisms were studied and considered in the energy estimations. The results show how the energy consumption scales with the number of qubits and how the most relevant parameters required for qubit stabilization, gate implementation, and error correction codes contribute to the overall energy usage. An optimization method was developed to tune these parameters with the goal of minimizing energy consumption while maintaining qubit fidelities above a given threshold. Additionally, a comparative study with state-of-the-art classical computers indicates a potential quantum energetic advantage for systems with more than 26 qubits, assuming cryogenic systems operating at Carnot efficiency, with this energetic advantage arising before any computational advantage. This behavior persists even when realistic cryogenic systems and control electronics are taken into account.
Low energy dissipation and ability to operate at low temperatures provide for Josephson junction circuits a niche as a support for low temperature devices. With high speed operation (Chen W. et al., 1999) capability the Josephson junction circuits make a prime candidate for applications which are difficult to engineer with existing CMOS technology. The development of Josephson junction technology took a major turn for the better with the invention of the Rapid-Single-Flux-Quantum (RSFQ) devices (Likharev K.K. et al., 1991), an improvement over voltage biased Josephson Junctions logic which were plagued with the junction switching and reset problems. The modern applications of SFQ circuits extend to a larger range of temperature operation and the applications vary from low temperature magnetic sensor, to high speed mixed signal circuits, voltage and current standards (Turner C.W. et al., 1998), and auxiliary components for quantum computing circuits. Most of the SFQ circuits are fabricated with Niobium, but Aluminum based circuits are being used for quantum gates (Nielsen M.A. et al., 2000) and qubit operations. SFQ circuits based on Magnesium di-Boride junctions are being developed for higher temperature operations (Tahara S. et al., 2004). Predominantly most of the Josephson junction circuits today are operated at around 4K. All the circuits are optimized usually for liquid helium temperatures, so the circuits operated in helium bath Dewars or cryostat's do not experience any temperature gradients or drift effects which can affect the operating margins. With the improvement in the fabrication technology and soft-wares for SFQ circuit technology, the designing complex circuits have become easier. Complex Circuits with over 20K junctions such digital synthesizer and digital RF Trans-receiver have already been demonstrated (Oleg M.A. et al., 2011). Development of circuits over 100K junctions are actively under progress. However, with enormously large circuits, power requirements also increase. Looking at the range of applications and complexity of the problems of energy minimization, we try to look at the problem in two approaches. One for large complex circuits, we try to reduce the power bias itself, or the overall load of current that is supplied