Low energy dissipation and ability to operate at low temperatures provide for Josephson junction circuits a niche as a support for low temperature devices. With high speed operation (Chen W. et al., 1999) capability the Josephson junction circuits make a prime candidate for applications which are difficult to engineer with existing CMOS technology. The development of Josephson junction technology took a major turn for the better with the invention of the Rapid-Single-Flux-Quantum (RSFQ) devices (Likharev K.K. et al., 1991), an improvement over voltage biased Josephson Junctions logic which were plagued with the junction switching and reset problems. The modern applications of SFQ circuits extend to a larger range of temperature operation and the applications vary from low temperature magnetic sensor, to high speed mixed signal circuits, voltage and current standards (Turner C.W. et al., 1998), and auxiliary components for quantum computing circuits. Most of the SFQ circuits are fabricated with Niobium, but Aluminum based circuits are being used for quantum gates (Nielsen M.A. et al., 2000) and qubit operations. SFQ circuits based on Magnesium di-Boride junctions are being developed for higher temperature operations (Tahara S. et al., 2004). Predominantly most of the Josephson junction circuits today are operated at around 4K. All the circuits are optimized usually for liquid helium temperatures, so the circuits operated in helium bath Dewars or cryostat's do not experience any temperature gradients or drift effects which can affect the operating margins. With the improvement in the fabrication technology and soft-wares for SFQ circuit technology, the designing complex circuits have become easier. Complex Circuits with over 20K junctions such digital synthesizer and digital RF Trans-receiver have already been demonstrated (Oleg M.A. et al., 2011). Development of circuits over 100K junctions are actively under progress. However, with enormously large circuits, power requirements also increase. Looking at the range of applications and complexity of the problems of energy minimization, we try to look at the problem in two approaches. One for large complex circuits, we try to reduce the power bias itself, or the overall load of current that is supplied
Low energy dissipation and ability to operate at low temperatures provide for Josephson junction circuits a niche as a support for low temperature devices. With high speed operation (Chen W. et al., 1999) capability the Josephson junction circuits make a prime candidate for applications which are difficult to engineer with existing CMOS technology. The development of Josephson junction technology took a major turn for the better with the invention of the Rapid-Single-Flux-Quantum (RSFQ) devices (Likharev K.K. et al., 1991), an improvement over voltage biased Josephson Junctions logic which were plagued with the junction switching and reset problems. The modern applications of SFQ circuits extend to a larger range of temperature operation and the applications vary from low temperature magnetic sensor, to high speed mixed signal circuits, voltage and current standards (Turner C.W. et al., 1998), and auxiliary components for quantum computing circuits. Most of the SFQ circuits are fabricated with Niobium, but Aluminum based circuits are being used for quantum gates (Nielsen M.A. et al., 2000) and qubit operations. SFQ circuits based on Magnesium di-Boride junctions are being developed for higher temperature operations (Tahara S. et al., 2004). Predominantly most of the Josephson junction circuits today are operated at around 4K. All the circuits are optimized usually for liquid helium temperatures, so the circuits operated in helium bath Dewars or cryostat's do not experience any temperature gradients or drift effects which can affect the operating margins. With the improvement in the fabrication technology and soft-wares for SFQ circuit technology, the designing complex circuits have become easier. Complex Circuits with over 20K junctions such digital synthesizer and digital RF Trans-receiver have already been demonstrated (Oleg M.A. et al., 2011). Development of circuits over 100K junctions are actively under progress. However, with enormously large circuits, power requirements also increase. Looking at the range of applications and complexity of the problems of energy minimization, we try to look at the problem in two approaches. One for large complex circuits, we try to reduce the power bias itself, or the overall load of current that is supplied
Josephson Junction (JJ) based superconductor logic families have been proposed and implemented to process analog and digital signals [1] for its low energy dissipation and ultrafast switching speed. Thanks to its construction of resistance-less wires and ultrafast switches, it can operate at clock frequencies of several tens of gigahertz and even hundreds of thousands of times as energy efficient as its CMOS counterparts. It has been perceived to be an important candidate to replace stateof-the-art CMOS due to the superior potential in operation speed and energy efficiency, as recognized by the U.S. IARPA C3 and SuperTools Programs and Japan MEXT-JSPS Project. The design and fabrication of superconducting circuits have already been established [2]-[4]. In addition, a prototype superconducting microprocessor "Core 1" has been demonstrated in 2004 [3], which is able to execute instructions at a high clock frequency of several tens of gigahertz, and with extremely low-power dissipation. These achievements make superconducting electronics highly promising for future high-performance computing applications. As one of the most matured superconducting technology, the Rapid-Single-Flux-Quantum (RSFQ) technology is proposed by K. Likharev, O. Mukhanoc, V. Semenov in 1985 [1]. Despite its capability to be operated at an ultra-high speed of hundreds of GHz while maintaining extremely low switching energy (10^-19 J), it suffers from an increasing static power due to on-chip resistors that are required for constant DC bias supply for the main RSFQ circuit. Numerous methods have been proposed to resolve the static power dissipation problem of RSFQ, including low-voltage RSFQ (LV-RSFQ) [5], reciprocal quantum logic (RQL) [6], LRbiased RSFQ [7] and energy-efficient single-flux quantum (eSFQ) [8]. The Adiabatic Quantum-Flux-Parametron (AQFP) technology, on the other hand, uses AC bias/excitation currents as both multiphase clock signal and power supply [9] to mitigate the power consumption overhead of DC bias while operating at a frequency of few GHz. Consequently, AQFP is remarkably energy efficient compared to RSFQ, albeit operating at a lower frequency. The energy-delay-product (EDP) of the AQFP circuits fabricated using processes such as the AIST standard process 2 (STP2) and the MIT-LL SFQ process [10], [11], is at least 200 times smaller than those of the other energy-efficient superconductor logics and is only three orders of magnitude larger than the quantum limit [9]. Physical testing results of an AQFP 8-bit carry-look-ahead adder and large scale circuits consisting up-to 10,000 AQFP logic gates have demonstrated the AQFP being a promising technology that is robust against circuit parameter variations [12]. Despite the high application potential of AQFP in VLSI circuits, a systematic, automatic synthesis framework for AQFP is imminent. There are two features of AQFP that restrict conventional CMOS synthesis methods being directly applied on AQFP. In spite of And-Or-Inverter(AOI) based representation, which conventional CMOS circuits highly relies on, AQFP circuits prefer majority gates. In fact, its two inputs AND and OR gates are also built with three inputs majority gate with one input being constant. In addition, given its clock-synchronized data propagation nature, AQFP technology requires all inputs to any gate having equal delay. In order to meet this balanced timing requirement, splitters and buffers need to be inserted to the circuit. As a matter of fact, some circuit size can be doubled even with optimum amount of buffers and splitters inserted. The buffer and splitter insertion method can have a huge impact on the overall resource consumption. As the design complexity increases, an unoptimized buffer and splitter insertion method could result in huge amount of unnecessary buffers and splitters added. In addition to a complete synthesis framework, an Integrated Development Environment (IDE) for AQFP design is also lacking. It is imminent to have an IDE for AQFP integrating tools that offer schematic and layout editor, simulation and analysis for better and more efficient AQFP design flow. In this paper, we propose a complete design tool for AQFP design including an Integrated Development Environment (IDE), a complete majority based synthesis framework and a buffer and splitter insertion framework. we propose a majority gates synthesis framework for AQFP circuits that is capable of converting any AOI netlist to its corresponding MAJ netlist by mapping all feasible three-input sub-netlists to corresponding MAJ based implementations. In addition, we also propose an automated buffer and splitter insertion method that is capable of adding the optimum amount of buffers and splitters to any given gate-level netlist. The proposed method can find the minimum amount of buffers and splitters to inserted to achieve equal delay with any library limitation on the size of splitters. Experimental results suggest that the proposed methods can deliver very optimized results. The majority conversion tool can reduce circuit size by an average of 16:47% and delay by 30:21% in average. The buffer and splitter insertion tool only introduces an average of 14:24% overhead in size and 4:70% delay with splitter fanout size limited to 4 compared to an unachievable ideal results with no limitations on splitter fan-out size. Overall, the balanced design in majority gates can be reduced by 23:85% and 29:54% in size and delay compared to its AND/OR/Inverter implemented counterpart.
The authors argue that superconducting digital electronics is the future trend for high-speed and low-power applications. Low-T/sub c/ technology based on stable Nb-AlO/sub x/-Nb tunneling junctions has been successful in constructing most of the digital circuit logic elements. A four-stage shift register constructed with latching logic operated up to 4 GHz with a power consumption of about 60 mu W per gate. A 12-b analog-digital coverter constructed with a single flux quantum (SFQ) logic showed proper operation with the total power dissipated being only about 100 mu W. Fabrication of Josephson tunneling junctions with high-T/sub c/ materials has been tougher than with low-T/sub c/ materials. However, recently developed very high speed rapid single flux quantum (RSFQ) logic circuits can be applied to weak link type junctions fabricated with YBa/sub 2/Cu/sub 3/O/sub 7-x/ films. Simulations of the various circuits with weak link type junctions, e.g., shift registers, analog-digital converters, etc., show fast operation and reasonable margins. Applications of similar concepts can be applied to NbN circuits operating at above 10 K.>
Rapid Single Flux Quantum (RSFQ) Josephson-junction technology is capable of processing digital data at sub-terahertz frequencies while dissipating almost negligible power. At the present time one can routinely simulate, optimize, design, manufacture, and test an elementary RSFQ logic/memory cell consisting of dozens of Josephson junctions. Furthermore, a number of relatively complex (few hundred to few thousand Josephson junctions) digital circuits were designed and successfully tested. Moreover we know how to implement several RSFQ systems (including analog-to-digital and digital-to-analog converters, digital SQUIDs for supersensitive magnetometry, and digital autocorrelator for radioastronomy) which would far outperform their currently available and even prospective semiconductor counterparts. In order to implement more complex RSFQ systems, including high-performance digital signal processors and general purpose computers there are a number of technical problems to solve. The issues include making full use of on-chip sub-terahertz processing in conditions when inter-chip data/clock exchange speed is bound by bandwidth of the order of a few Gbps/pin. I present the current know-how of the field, and formulate the questions that need to be solved before the RSFQ technology becomes a major workhorse of high-performance computation.
Rapid single flux quantum (RSFQ) electronics is based on the Josephson junction as an active switching element. In standard RSFQ circuits its switching energy is much lower than the static power consumption caused by the resistive current distribution network. Due to this thermal heating of the chip, the maximum number of junctions on a single chip is limited to about 1 million. The frequency-dependent contribution to power dissipation from junction switchings is only about 2 percent of the static one. This fact limits the direct construction of VLSI systems for high-performance computing as well as small-scale circuit applications in the vicinity of ultra-sensitive detectors or even quantum circuits. We present an assessment of different approaches for reducing the static power consumption by investigating the potential of inductive bias distribution networks as well as reduced critical currents. We analyse the operation stability of simple digital circuits with 5 times smaller critical currents at 4.2 K. The combination of the reduced critical currents and inductive biasing can provide digital superconductive circuits with significantly reduced static power consumption.
Superconducting single flux quantum (SFQ) technology is well known for digital logic operations below 4.2 K, which are compatible with the Josephson junction qubit. Operation speed and signal sensitivity of circuits in SFQ are also sufficient to control qubits. Therefore, the SFQ circuit is a candidate technology for multiple qubit control. However, the self-heating effect of the SFQ circuit is a potential barrier to development of an SFQ-supported multiple qubit system because the qubit operating temperature is lower than the conventional 4.2 K. The multi-chip approach is a possible solution because the qubit chip can be thermally isolated from the SFQ circuitry. We report on recent progress in SFQ circuit and packaging technology for operation at sub-Kelvin temperatures. As for multi-chip module technology, a test sample of the multi-chip module shows good reliability of electrical connections between chips, and each solder bump has a bandwidth wide enough for signal transmission. We have designed lower power SFQ circuits for sub-Kelvin temperatures. The critical currents of Josephson junctions were scaled down, inductances were scaled up, and bias voltage was reduced to make power consumption lower. Based on our fabrication technology, critical current densities were optimized by considering trade-off relations between fabrication availability and operation speed. We successfully confirmed its correct operations at around 0.35 K. The combination of the multi-chip module and optimized SFQ circuits is very effective way of controlling qubit.
Single flux quantum (SFQ) electronics is extremely fast and has very low on-chip power dissipation. SFQ VLSI is an excellent candidate for high-performance computing and other applications requiring extremely high-speed signal processing. Despite this, SFQ technology has generally not been accepted for system implementation. We argue that this is due, at least in part, to the use of outdated tools to produce SFQ circuits and chips. Assuming the use of tools equivalent to those employed in the semiconductor industry, we estimate the density of Josephson junctions, circuit speed, and power dissipation that could be achieved with SFQ technology. Today, CMOS lithography is at 90?65?nm with about 20 layers. Assuming equivalent technology, aggressively increasing the current density above 100?kA?cm?2 to achieve junction speeds approximately 1000?GHz, and reducing device footprints by converting device profiles from planar to vertical, one could expect to integrate about 250?M Josephson junctions cm?2 into SFQ digital circuits. This should enable circuit operation with clock frequencies above 200?GHz and place approximately 20?K gates within a radius of one clock period. As a result, complete microprocessors, including integrated memory registers, could be fabricated on a single chip.