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IEEE Vehicular Technology Conference

On Optimized Uniform Quantization for SC Decoder of Polar Codes

Zhengming Shi, Kai Chen, Kai Niu

Published Sep 1, 2014• 5 citations
Publisher

Abstract

Polar codes have a regular recursive structure which is feasible for hardware implementation in practice. Quantization is a critical issue in hardware implementation. In this paper, a quantization scheme for successive-cancellation (SC) decoding of polar codes is proposed based on the equivalent channel cutoff rate optimization. Moreover, a modified Gaussian approximation (GA) method exploiting the cutoff rate maximizing criterion is brought forward to construct polar codes and estimate frame error rate (FER) performance under the quantized decoding algorithms. Utilizing the modified GA, the optimal quantization bits can be determined. Simulation results demonstrate that a 6-bit uniform quantized SC decoder could achieve a near floating point performance. Compared with the existing results in the published literature, the proposed method consumes no more than 4.5 quantization bits and performs better.

DOI
10.1109/vtcfall.2014.6966081

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Polar codes have a regular recursive structure which is feasible for hardware implementation in practice. Quantization is a critical issue in hardware implementation. In this paper, a quantization scheme for successive-cancellation (SC) decoding of polar codes is proposed based on the equivalent channel cutoff rate optimization. Moreover, a modified Gaussian approximation (GA) method exploiting the cutoff rate maximizing criterion is brought forward to construct polar codes and estimate frame error rate (FER) performance under the quantized decoding algorithms. Utilizing the modified GA, the optimal quantization bits can be determined. Simulation results demonstrate that a 6-bit uniform quantized SC decoder could achieve a near floating point performance. Compared with the existing results in the published literature, the proposed method consumes no more than 4.5 quantization bits and performs better.
A new decoding scheme aided by simulated annealing algorithm is proposed to further improve the decoding performance of successive cancellation (SC) for polar codes at the short block. We use simulated annealing to revise the decoding result of SC which cannot pass the CRC check. To generate the new neighbors, the decoder flips one bit from the set of the least unreliable information bits each time in the estimated source vector of SC decoding. Euclidean distance is used to measure the gap between the new neighbor solution and the received word so that the decoder can obtain a global optimal solution. Simulation shows that the proposed decoder has a performance gain about 0.5 dB in terms of frame error rate (FER) under short blocks in the additive white Gaussian noise (AWGN) channel compared to other basic decoders, while keeping a low time cost through a parameter tuning process.
Polar codes have recently found application as error correction codes for the control information in 5 G wireless communication. Stringent requirements for decoding latency, power consumption, and communication reliability demand efficient hardware implementation of communication modules. One of the key aspects of efficient hardware implementation is a robust quantization scheme. In this paper, we present an empirical approach to analyzing quantization for the Cyclic Redundancy Check-Aided Successive Cancellation List (CA-SCL) decoding algorithm, which is used in the 5 G standard. The paper gives detailed quantization analysis of the CA-SCL algorithm for 11-bit CRC and 4 lists. We proposed a quantization scheme with decoding performance within 0.1 dB of the floating point performance for positive Signal-to-noise ratios (SNRs). It is shown that a decoder with one extra bit achieves performance within 0.1 dB of the floating-point model over a wide range of SNRs and code rates.
This paper presents a successive cancellation (SC) decoding of polar codes modified for insertion/deletion/substitution (IDS) error channels, in which insertions and deletions are described by drift values. The recursive calculation of the original SC decoding is modified to include the drift values as stochastic variables. The computational complexity of the modified SC decoding is O (D3) with respect to the maximum drift value D, and O (N log N) with respect to the code length N. The symmetric capacity of polar bit channel is estimated by computer simulations, and frozen bits are determined according to the estimated symmetric capacity. Simulation results show that the decoded error rate of polar code with the modified SC list decoding is lower than that of existing IDS error correction codes, such as marker-based code and spatially-coupled code.
Representing continuous values by streams of random binary bits, stochastic decoding has shown advantages in both hardware efficiency and fault tolerance, therefore has been widely adopted by iterative decoding of error correction codes such as low-density parity-check (LDPC) codes and so on. Recently, polar codes, the first codes that can provably achieve the capacity of symmetric binary-input discrete memoryless channels (B-DMCs), have drawn a lot of attentions from both academia and industry. Although, polar codes with list successive cancellation (SC) decoding can outperform several best-known LDPC codes even within high error-rate regions, the linearly increasing hardware complexity makes its efficient implementation difficult. To this end, the stochastic list SC polar decoding algorithm is proposed in this paper to provide a good tradeoff between performance and complexity. In order to increase the decoding performance of stochastic list SC polar decoder, doubling probability approach is presented. The corresponding hardware architecture is also given. The approximate doubling approach is employed to facilitate the efficient implementation. Implementation results have shown that the proposed stochastic list SC polar decoder can achieve a good trade-off between performance and complexity.
Polar codes are a class of codes discovered recently, which are proved to have capacity-achieving performance. The hardware implementations of successive cancellation (SC) decoding and List SC decoding are increasing dramatically now. However, throughput of these hardware structures remain to be improved on the one hand. On the other hand, stochastic computation is now wildly used because it uses simple structures to implement complicated mathematical operations and thus improves the throughput. This paper extends the application of stochastic computation to the decoding of polar codes. A family of SC decoders based on stochastic computation are proposed, including decoders based on bipolar stochastic computation(BSC-SC), low bits stochastic computation(LBSC-SC) and improved stochastic computation(ISC-SC). These methods have high generality and improve the throughput over SC decoder while having 0.5dB loss in decoding performance. The proposed 32-bit ISC-SC decoder has a better decoding accuracy and improves throughput over BSC-SC. It also reduces the hardware cost and latency compared to LBSC-SC decoder.
In this paper, we propose a low complexity hybrid ordered statistics decoding (OSD) successive cancellation (SC) decoding algorithm for the polar codes. By replacing smaller size SC decoder with OSD decoder, we can improve the error correcting performance of the SC algorithm. The size of the OSD decoder can be changed to control the trade-off between the decoding complexity and the error correcting performance of the proposed algorithm. We also provide a method to further simplify the proposed algorithm. Simulation results show that the proposed algorithm offers about 0.3 dB gain comparing to the SC at target bit error rate (BER) 10-5with code length N = 1024, 512,256 and code rate R = 1 /3. The impact of the OSD size is also simulated and analyzed.