A new decoding scheme aided by simulated annealing algorithm is proposed to further improve the decoding performance of successive cancellation (SC) for polar codes at the short block. We use simulated annealing to revise the decoding result of SC which cannot pass the CRC check. To generate the new neighbors, the decoder flips one bit from the set of the least unreliable information bits each time in the estimated source vector of SC decoding. Euclidean distance is used to measure the gap between the new neighbor solution and the received word so that the decoder can obtain a global optimal solution. Simulation shows that the proposed decoder has a performance gain about 0.5 dB in terms of frame error rate (FER) under short blocks in the additive white Gaussian noise (AWGN) channel compared to other basic decoders, while keeping a low time cost through a parameter tuning process.
A new decoding scheme aided by simulated annealing algorithm is proposed to further improve the decoding performance of successive cancellation (SC) for polar codes at the short block. We use simulated annealing to revise the decoding result of SC which cannot pass the CRC check. To generate the new neighbors, the decoder flips one bit from the set of the least unreliable information bits each time in the estimated source vector of SC decoding. Euclidean distance is used to measure the gap between the new neighbor solution and the received word so that the decoder can obtain a global optimal solution. Simulation shows that the proposed decoder has a performance gain about 0.5 dB in terms of frame error rate (FER) under short blocks in the additive white Gaussian noise (AWGN) channel compared to other basic decoders, while keeping a low time cost through a parameter tuning process.
In this paper, two decoding algorithms based on Successive-Cancellation (SC) are proposed to improve the error-correction performance of cyclic redundancy check (CRC)-aided polar codes while aiming for a low-complexity implementation. Comparisons with Dynamic SC Flip (DSCF) and SC Perturbation (SCP) are carried out since the proposed DSCF and Perturbation (DSCFP) and Perturbed DSCF (PDSCF) algorithms combine both methods. The analysis includes comparisons with several code lengthsNand various number of decoding attemptsTmax. ForN=1024and the coding rateR=1/2, the DSCF and the SCP algorithms withTmax=17are bested by approximately 0.1 dB at block-error rate (BLER) of 0.001. At BLER = 10−6and forTmax=64, the gain is of 0.375 dB and > 0.5 dB with respect to DSCF and SCP, respectively. At high signal-to-noise ratio, the average computational complexity of the proposed algorithms is virtually equivalent to that of SC.
As an improved version of successive cancellation (SC) polar decoder, an SC stack (SCS) decoder has been proposed for performance improvement. However, the existing SCS polar decoder suffers a lot from high time complexity at low signal-to-noise ratio (SNR) region and space complexity compared with the SC decoder. To this end, two improved decoders are proposed to reduce time and space complexity in both low and high SNR regions. The first one is the segmented cyclic redundancy check (CRC)-aided SCS (SCA-SCS) decoder, which is based on segmented parity checkers. The second one is the adaptive SCS (ASCS) decoder, which has the flexibility of stack depth and searching width. Furthermore, a channel condition estimator is proposed to select appropriate decision criteria for different SNR scenarios. Results have shown that for the polar code of length 1024 and rate 1/2, two improved SCS decoders can perform better than the traditional SCS decoder. The proposed SCA-SCS decoder and the ASCS decoder can achieve 10.8% and 11.42% time complexity reduction and 31.68% and 60.85% space complexity reduction on average over binary-input additive white Gaussian noise channels (BI-AWGNCs), respectively. Efficient parallel hardware architecture of the SCS polar decoder is first proposed and implemented with 90- and 65-nm technologies. Results have verified its advantages over the state of the art (SOA).
Polar codes have a regular recursive structure which is feasible for hardware implementation in practice. Quantization is a critical issue in hardware implementation. In this paper, a quantization scheme for successive-cancellation (SC) decoding of polar codes is proposed based on the equivalent channel cutoff rate optimization. Moreover, a modified Gaussian approximation (GA) method exploiting the cutoff rate maximizing criterion is brought forward to construct polar codes and estimate frame error rate (FER) performance under the quantized decoding algorithms. Utilizing the modified GA, the optimal quantization bits can be determined. Simulation results demonstrate that a 6-bit uniform quantized SC decoder could achieve a near floating point performance. Compared with the existing results in the published literature, the proposed method consumes no more than 4.5 quantization bits and performs better.
An improved CA-SCL (CRC-Aided Successive Cancellation List) decoding algorithm for Polar codes is proposed in this paper. By introducing the global cyclic redundancy check and local parity check, a lower bit error rate is obtained comparing with the known results. The new algorithm constructs a prune decoding path by the parity check in the local processing. Since the parity check can only detect an odd number of errors, the global CRC is used to increase the error detection ability and the decoding accuracy. The performance of the improved decoding algorithm is better than the known results, especially when the code length is either less than or equal to 512, and the code rate is not greater than 0.5 in case of the signal-to-noise ratio (SNR) higher than 3dB. In particular, when the code length is 256 with code rate of 0.5 and decoding list size of 32 under the condition of bit error rate 10-5on the AWGN channel, the proposed algorithm has around 0.25dB and 0.55dB performance gain comparing with that of the CA-SCL and SCL algorithms, respectively.
Novel successive cancellation list (SCL) decoding schemes of Polar codes by exploiting the error correction (EC) capability of the cyclic redundancy check (CRC) codes are proposed in this paper. Different from the schemes in the literature that only considered the error detection capability of CRC, the proposed schemes aim to improve the performance of CRC-aided Polar decoding to the most by benefiting from the potential EC capability of CRC. Specifically, we first propose a basic decoding scheme, named CRC error-correction-aided successive cancellation list (CRC-EC-SCL) decoding, by introducing the look-up-table-based CRC EC method into the Polar SCL decoding process. Then, based on the basic scheme, we further propose the segmented-CRC-EC-SCL decoding scheme. By segmented-CRC, the information block is divided into multiple segments and each segment is attached with a shorter CRC sequence. By conducting the CRC-EC-aided coding for each of the segments, multiple erroneous bits can be corrected early and error propagation can, thus, be efficiently suppressed. The simulation results show that both of the proposed decoding schemes have a significant performance gain over the classic CRC-EC-SCL decoding scheme. Especially for the segmented-CRC-EC-SCL, the performance gain at a frame error rate of 10−4is about 0.4 dB. Moreover, the average computation complexity of the segmented-CRC-EC-SCL is close to the classic scheme.
Successive cancellation (SC) decoding of polar codes may bring about error propagation that needs to be mitigated. In this paper, we present a new SC Flipping (SCFlip) decoder, named bit error rate (BER) evaluation based SCFlip (BER-SCFlip), which can accurately target the first error bit and correct it with a high probability. Thus, a high error correction capability and a low decoding complexity can be achieved. First, we propose a new criterion to find out the most suspicious error bit. Those non-frozen bits that have higher decoding BERs derived from log-likelihood-ratios (LLRs) after SC decoding than the corresponding expected ones estimated via Gaussian Approximation (GA), are collected into the flip-bits set. These candidate bits will be flipped one by one according to their SC decoding orderings in extra decoding attempts until the decoded codeword passes cyclic redundancy check (CRC) or a predetermined maximum number of extra attempts is reached. We then propose an extended version of BER-SCFlip, named BER-SCFlip-w with the capability to correct up to w error bits in each extra decoding attempt. By combining our criterion for the flip-bits selection with that of Dynamic SCFlip (D-SCFlip), the proposed BER-SCFlip-w significantly reduces decoding complexity and latency while maintaining the superior error-correction performance close to that of D-SCFlip-w. The simulation results show that the proposed schemes are competitive among existing SCFlip algorithms and could achieve the error-correction performance approaching that of CRC-aided SCL decoding under list size L = 16 while maintaining low complexity.