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Journal of Signal Processing Systems

Low Complexity Decoder Architecture for Low-Density Parity-Check Codes

Daesun Oh, Keshab K. Parhi

Published May 29, 2008• 4 citations
Publisher
DOI
10.1007/s11265-008-0231-5

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Introduction of Low-density Parity-Check decoding Algorithm design

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•Jan 1, 2004•1 citation
In this paper, a modified WiMAX Low-Density Parity-Check (LDPC) codes for realistic LDPC coding system architectures is presented. The LDPC code, which is a special class of quasi-cyclic LDPC (QC-LDPC), has an efficient encoding algorithm owing to the simple structure of their parity-check matrices. A proposed distribution of irregular parity-check matrix for the modified WiMAX LDPC is developed so that we can obtain a low-complexity architecture design, and achievable circuit implementation. The modified WiMAX LDPC code decoding employs the iterative min-sum algorithm (MSA) and its decoder architecture design uses the bit node unit (BNU) and check node unit (CNU). Different word-length of hardware design for LDPC decoder can be simulated. Therefore, the word-length with 8-bit is enough for hardware implementation.
In this paper, the authors propose an efficient highly-parallel decoder architecture using partially overlapped decoding scheme for quasi-cyclic (QC) low-density parity-check (LDPC) codes, which leads to reduction in hardware complexity and power consumption. Generally, due to the regularly structured parity-check matrix H of QC LDPC codes, the message updating computations in the check node unit (CNU) and the variable node unit (VNU) can be efficiently overlapped, which increases the decoding throughput by maximizing the hardware utilization efficiency (HUE). However, the partially overlapped decoding scheme cannot be used to design a highly-parallel decoding architecture for high-throughput applications. For (3, 5)-regular QC LDPC codes, our proposed method could reduce the hardware complexity by approximately 33% for the CNU and 20% for the VNU in the highly-parallel decoder architecture without any performance degradation. In addition, the power consumption can be minimized by reducing the total number of memory accesses for updated messages.