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National Conference on Communications

Novel hardware implementation of LLR-based non-binary LDPC decoders

Lava Bhargava, Ranjan Bose, M. Balakrishnan

Published Feb 1, 2013• 3 citations
Publisher

Abstract

Binary Low Density Parity Check (LDPC) codes are known to have performance approaching capacity utilization for large block lengths. For short and medium term block lengths, the codes have lower capacity utilization and poorer BER performance due to cycles in the codes. The non-binary LDPC codes have started attracting attention for short and medium length code implementations, which is a requirement for standards like Wi-Fi applications. Current implementations of non-binary LDPC codes focus on serial or partly parallel implementation due to hardware complexity and chip size. We propose a fully parallel implementation for two algorithms. The algorithms are the SPA algorithm with max* function and a sub-optimal form of this called as max implementation. The max implementation has a lower hardware cost and a low performance penalty. The area of sub-optimal max implementation is almost 32% less than that of max implementation. The clock for max is faster by 33%, as a result it has low latency and high throughput as compared to max* algorithm.

DOI
10.1109/ncc.2013.6487956

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Binary Low Density Parity Check (LDPC) codes are known to have performance approaching capacity utilization for large block lengths. For short and medium term block lengths, the codes have lower capacity utilization and poorer BER performance due to cycles in the codes. The non-binary LDPC codes have started attracting attention for short and medium length code implementations, which is a requirement for standards like Wi-Fi applications. Current implementations of non-binary LDPC codes focus on serial or partly parallel implementation due to hardware complexity and chip size. We propose a fully parallel implementation for two algorithms. The algorithms are the SPA algorithm with max* function and a sub-optimal form of this called as max implementation. The max implementation has a lower hardware cost and a low performance penalty. The area of sub-optimal max implementation is almost 32% less than that of max implementation. The clock for max is faster by 33%, as a result it has low latency and high throughput as compared to max* algorithm.
Non-binary low-density parity-check (NB-LDPC) codes can achieve better error-correcting performance than binary LDPC codes when the code length is moderate. For the first time, this paper proposes a partial-parallel decoder architecture based on the Min-max algorithm for quasi-cyclic NB-LDPC codes. A novel boundary tracking based scheme and corresponding architecture are developed to implement the elementary step of the check node processing. In addition, layered decoding is applied, and the hardware units are optimized to reduce the latency and area. This paper also introduces an overlapped method for the check node processing among different layers to further speed up the decoding. From complexity analysis, the proposed decoder with 5 iterations for a (837,726) code over GF(25) can easily achieve 60 Mbps throughput on ASIC devices. It is 40% more efficient than prior designs.
Low-Density Parity-Check (LDPC) codes have gained significant popularity recently and have been recommended for various wireless standards of the future. Non-binary LDPC codes provide all the well-known advantages of binary LDPC codes but allow for much shorter block lengths. The sum-product decoding algorithm for non-binary LDPC codes is too complex for efficient implementation. Hence, we have represented the sum-product algorithm in a novel log-domain form in terms of operators defined earlier in literature. This form greatly simplifies the key step in the check-node processing and allows us to replace a max* operation in the decoder by a max operation. This leads to a sub-optimal decoding algorithm which we propose in this paper.
Low density parity check (LDPC) codes over are an extension of binary LDPC codes with significantly higher performance. However, the computational complexity of the encoders/decoders for these codes is also higher. Hence there is a substantial lack of hardware implementations for LDPC over codes. This paper proposes a novel variation of the belief propagation algorithm for LDPC codes. The new algorithm results in a reduced hardware complexity when imple- mented in VLSI. The serial architecture of the novel decoding algorithm and two other algorithms for LDPC over are implemented on an FPGA. The results show that the proposed algorithm has substantial advantages over existing methods. We show that the implementation of LDPC over decoder is feasible for short to medium length codes. The additional com- plexity of the decoder is balanced by the superior performance of LDPC codes.
After the introduction of iterative coding, Low Density Parity Check (LDPC) codes have received a lot of attention due to their remarkable near Shannon-limit performance and practical decoder implementation. However, when employing an LDPC code for various applications, multiple issues do arise at the simulation, algorithm and implementation levels. The first issue is the performance evaluation of the iterative LDPC decoder in the very low Bit Error Rate (BER) regions. So far, no analytical tool has been developed to evaluate the performance of LDPC codes. Unfortunately standard Monte Carlo (MC) simulations cannot be used for performance estimation in these low BER regions due to prohibitive execution times. The second issue is the efficiency of the decoding algorithm. Due to the presence of short cycles in the bipartite graph, sum-product decoding algorithms lead to considerable performance loss for short block-length LDPC codes and produce error floors for longer codes. In addition, the iterative processing and estimation of soft probabilistic values with these algorithms result in very high computational complexity, which in turn impedes the adoption of LDPC codes for power constrained systems. Another prime objective is to design a high throughput decoder architecture which is capable of supporting multiple rates and variable code lengths within minimal area. This work aims to address and provide solutions to the above problems. As a solution to the performance estimation problem of LDPC codes, a highly efficient and novel fast BER simulation technique is developed. At the algorithm level, a performance improvement and error floor avoidance method is introduced, and a computationally efficient algorithm is developed for the sum-product decoding of LDPC codes. And finally, at the architecture level, a high throughput multi-rate variable code length implementation is presented which, when implemented, efficiently minimizes device resources while alleviating the routing complexity of the decoder.
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Because of their excellent error-correcting performance, low-density parity-check (LDPC) codes have recently attracted a lot of attention. In this paper, we are interested in the practical LDPC code decoder hardware implementations. The direct fully parallel decoder implementation usually incurs too high hardware complexity for many real applications, thus partly parallel decoder design approaches that can achieve appropriate trade-offs between hardware complexity and decoding throughput are highly desirable. Applying a joint code and decoder design methodology, we develop a high-speed -regular LDPC code partly parallel decoder architecture based on which we implement a -bit, rate- -regular LDPC code decoder on Xilinx FPGA device. This partly parallel decoder supports a maximum symbol throughput of Mbps and achieves BER at 2 dB over AWGN channel while performing maximum decoding iterations.