We present the results of low- and high-speed testing of a fully integrated all-digital one-bit RSFQ autocorrelator for short-millimeter and submillimeter wave spectrometry applications. The 16-channel device, complete with a 16/spl times/9 array of binary counters, on-chip double-oversampling quantizer and on-chip clock was operational at clock speeds of up to 11 GHz. The total number of Josephson junctions in the design was 1672, while the estimated total power dissipation was less than 0.1 mW. For high-speed testing of the device we have developed a specialized 16-channel room-temperature interface capable of real-time data acquisition at a 16 Mbps-per-channel output rate. Extensive high-speed on-chip testing of the autocorrelator has also been performed, both in analog and digital modes, in the latter mode with an additional on-chip clock controller. All chips were fabricated in HYPRES' standard 3.5 /spl mu/m-10 /spl mu/A//spl mu/m/sup 2/ Nb-trilayer process. We also present a new concept of a 128-channel autocorrelator system built on 8 independent identical chips with approximately 2,500 Josephson junctions per chip, i.e. within the reach of the present-day fabrication technology.
We present the results of low- and high-speed testing of a fully integrated all-digital one-bit RSFQ autocorrelator for short-millimeter and submillimeter wave spectrometry applications. The 16-channel device, complete with a 16/spl times/9 array of binary counters, on-chip double-oversampling quantizer and on-chip clock was operational at clock speeds of up to 11 GHz. The total number of Josephson junctions in the design was 1672, while the estimated total power dissipation was less than 0.1 mW. For high-speed testing of the device we have developed a specialized 16-channel room-temperature interface capable of real-time data acquisition at a 16 Mbps-per-channel output rate. Extensive high-speed on-chip testing of the autocorrelator has also been performed, both in analog and digital modes, in the latter mode with an additional on-chip clock controller. All chips were fabricated in HYPRES' standard 3.5 /spl mu/m-10 /spl mu/A//spl mu/m/sup 2/ Nb-trilayer process. We also present a new concept of a 128-channel autocorrelator system built on 8 independent identical chips with approximately 2,500 Josephson junctions per chip, i.e. within the reach of the present-day fabrication technology.
We present a new design of a Rapid Single-Flux-Quantum (RSFQ) all-digital one-bit autocorrelator for submillimeter spectrometry applications, featuring 4 GHz input signal bandwidth, double oversampling quantizer, and 16 Mbps-per-channel output rate. The delay line of the autocorrelator is based on a circular shift register with XOR gates performing multiplication of the delayed and undelayed single-bit signals at every stage. The multiplication results are accumulated by room-temperature electronics after being prescaled in on-chip binary counters consisting of 10 T flip-flops per stage. We report results of experimental testing of a 16-stage autocorrelator delay line with multiplication and for a linear array of 8 low-power T flip-flop binary counters, all fabricated in HYPRES' standard 3.5 /spl mu/m 1000 A/cm/sup 2/ Nb-trilayer process. We also discuss physical and technical limits of the minimal power dissipation in RSFQ circuits.
We present the design of a rapid single-flux-quantum all-digital 1-bit autocorrelator for submillimeter spectrometry applications, featuring 4-GHz input signal bandwidth, double oversampling quantizer, and 16-Mb/s-per-channel output rate. The correlator consists of a digital delay line with multiplication and an array of accumulators with parallel readout. We report experimental results for a three-stage delay line (294 Josephson junctions) and a 4/spl times/4 array of accumulators (288 Josephson junctions) fabricated in HYPRES' standard 3.5-/spl mu/m 1000-A/cm/sup 2/ Nb-trilayer process.
We describe the design of an oversampling single-flux-counting analog-to-digital converter with the estimated bandwidth of a few tens of MHz, based on Rapid Single-Flux-Quantum (RSFQ) devices. It consists of an input analog circuit, high-speed quantizer with an original analog/digital negative feedback loop, decimation (comb) filter, and supporting subsystems including clock distribution circuits, quantization signal conditioner, and output drivers. We have applied a new approach, the 'symmetrizing' negative feedback, to free the quantizer from the intrinsic hysteresis without dynamic range sacrifice. The 16-bit version of the system comprises about 1,500 Josephson junctions and consumes 1.2 mW of DC power, when implemented using Nb-trilayer technology with 1 kA/cm/sup 2/, 3.5 /spl mu/m Josephson junctions. All subsystems of the converter have been successfully tested and testing of the system as a whole is in progress.>
Rapid single flux quantum (RSFQ) 512-bit and 1024-bit shift registers have been demonstrated. These are the longest superconducting shift registers reported to date, employing 1045 and 2069 Josephson junctions, respectively. The circuit functionality has been confirmed with dc bias margins of +or-23% and +or-14% for the 512-bit and the 1024-bit shift registers, respectively. The 512-bit shift register has been tested to 20 GHz and 1024-bit register to 19 GHz using an external clock trigger with relative delay measurements at single and double SFQ clock frequencies. The shift registers with the same design have been used for successful implementation of the acquisition shift register (ASR) memory for the projected transient digitizer. These shift registers have the ability to acquire data at high speeds (gigahertz range), statically hold the acquired data, and then read-out the data into conventional room-temperature electronics at low speeds (megahertz range). A 32-bit ASR has been tested up to 18 GHz (the limit of our test setup), and a 1024-bit ASR-up to 16 GHz of acquisition rates, both at 33 MHz read-out frequency. Total power dissipation is about 1 mW for the 1024-bit circuit. The chips are fabricated using Hypres' Nb/AlO/sub x//Nb process with a junction critical current density of 1.0 kA/cm/sup 2/.>
We describe the design and implementation of a single-chip microprocessor based on LTS Rapid Single-Flux-Quantum (RSFQ) technology. Two such chips are to be used in a dual-processor module, being developed by a SUNY-TRW collaboration as a spin-off of the HTMT project. Each FLUX chip represents a simple 16-bit 2-way long-instruction-word (LIW) microprocessor with a pipelined instruction memory of 30-bit instructions, decode and issue units, 8 integer ALUs interlaced with 8 registers, and input/output ports through which two FLUX chips can communicate with each other at a 7-GHz communication rate over a multi-layer MCM. The FLUX instruction set consists of /spl sim/25 instructions. High performance is reached with a scalable design featuring (1) a very high clock rate, (2) localized, regular and ultrapipelined processing in registers with very short wires, (3) instruction-level parallelism utilization with bit-level resolution of data hazards. A 16-bit implementation of FLUX processor consists of /spl sim/90,000 Josephson junctions on a /spl sim/10 mm/spl times/15 mm chip area. Our estimates show that the processor will be able to operate at clock frequencies up to 20 GHz when implemented using TRW's 4 kA/cm/sup 2/, 1.75-/spl mu/m Nb-trilayer technology.
AbstractSuperconducting digital technology based on Rapid Single Flux Quantum (RSFQ) logic offers a 50 times faster clock rate and 100 times less on chip power consumption than today's mainstream semiconductor electronics. This technology is attractive for many applications and in particular for Digital Signal Processing (DSP). The applications of the RSFQ DSPs are numerous and include multi-user detection in spread spectrum system, channel equalization for Multi-in, Multi-out (MIMO) systems, and blind detection and signal tracking for signal intelligence.At Chalmers we are developing a hybrid DSP with target performance of 30 giga operations per second. It consists of an RSFQ Multiply Accumulate unit (MAC), RSFQ fast cache memory, and an external semiconductor memory. The development of the complex high speed cryogenic digital system requires interface, packaging and testing solutions. The main difficulties are due to the 4 K operational temperature, the high magnetic field sensitivity of the RSFQ circuits, the multi-channel high bandwidth interface required in the hybrid architecture, and the high speed RSFQ digital core. The key steps towards addressing each of these problems are the subject of this thesis. The main emphasis is put on the experimental testing and interfacing of superconductor electronics. A large part of the work is connected to the experimental verification of DSP components and their incremental improvement towards functionality. The RSFQ circuits tested were fabricated using the four-metal layer VLSI processes available from NGST(8 kA/cm^2 Josephson junction critical current) and HYPRES (both 1 kA/cm^2 and HYPRES 4.5 kA/cm^2. The main results of the work are demonstrations of the RSFQ cache memory with more than 2,000 Josephson junctions, 33.5 GHz operation of the digital clock controller, and 20.48 GHz operation of the autocorrelator. In addition, various experiments have been done for investigation of parasitic effects in RSFQ circuits such as flux trapping and influence of the high current bias lines.At the final stage of the work, a unique high bandwidth 4 K cryocooler based experimental setup has been developed. The system, developed in close cooperation with Hypres Inc. USA, has 40 high speed I/Os with bandwidth of 2 Gbps, 64 DC bias channels, 4 high frequency clock lines, and 4 auxiliary control lines. It supports exchangeable test units for 10 mm x 10 mm and 20 mm x 20 mm Multi Chip Module (MCM) carriers. The availability of such a system is critical to demonstration of the hybrid DSP prototype and future commercialization.